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Bunnik, Netherlands

Vecchi F.,Istituto Universitario Studi Superiori Of Pavia | Bozzola S.,Broadcom Netherlands BV | Temporiti E.,STMicroelectronics | Guermandi D.,Broadcom Netherlands BV | And 6 more authors.
IEEE Journal of Solid-State Circuits | Year: 2011

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. © 2011 IEEE. Source


Bult K.,Broadcom Netherlands BV | Lin C.-H.,Broadcom Corporation | Van Der Goes F.,Broadcom Netherlands BV | Westra J.,Broadcom Netherlands BV | And 5 more authors.
Analog Circuit Design - Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, AACD 2011 | Year: 2012

A 12b 2.9GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < -60dBc beyond 1 GHz while driving a 50 Ω load with an output swing of 2.5Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with "always-ON" biasing. © 2012 Springer Science+Business Media B.V. Source


Vecchi D.,Broadcom Netherlands BV | Mulder J.,Broadcom Netherlands BV | Van Der Goes F.M.L.,Broadcom Netherlands BV | Westra J.R.,Broadcom Netherlands BV | And 4 more authors.
IEEE Journal of Solid-State Circuits | Year: 2011

This paper presents a 12-bit dual-residue pipeline ADC allowing the use of low gain and low bandwidth residue amplifiers to achieve 59 dB peak SNDR at 800 MSample/s. The dual-residue architecture is insensitive to the open-loop gain and the bandwidth of the residue amplifiers. However, their offset limits the accuracy of the entire ADC and therefore a background offset calibration technique was implemented. The high sampling speed was obtained through four times interleaving, requiring gain and offset calibration between the interleaved ADC lanes. The ADC was realized in a standard 40 nm CMOS technology, operates from a dual 1 V/2.5 V power supply, utilizes an input range of 1.2 V peak-to-peak differential, and consumes 105 mW. © 2011 IEEE. Source


Westra J.R.,Broadcom Netherlands BV | Mulder J.,Broadcom Netherlands BV | Ke Y.,Broadcom Netherlands BV | Vecchi D.,Broadcom Netherlands BV | And 7 more authors.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 | Year: 2014

The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers. It also shows how these considerations are implemented in a practical design. At frequencies up to 400MHz, the transceiver presented in this paper achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR and >60dB receiver SFDR. Achieving a bit-error-rate (BER) better than 10-15, it dissipates less than 1.75W at full 10Gb/s traffic over a 100m cable, which is the lowest power for a 10GBASE-T AFE published to date. © 2014 IEEE. Source

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