Ahmed I.,University of Toronto |
Mulder J.,Broadcom Netherlands |
Johns D.A.,University of Toronto
IEEE Journal of Solid-State Circuits | Year: 2010
A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 μu CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits. © 2010 IEEE.
Van Der Goes F.,Broadcom Netherlands |
Ward C.M.,Broadcom Netherlands |
Astgimath S.,Cirrus Logic Inc. |
Yan H.,Broadcom Netherlands |
And 5 more authors.
IEEE Journal of Solid-State Circuits | Year: 2014
This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resulting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power efficiency include the choice of ADC architecture, integrator-based amplifiers used for noise filtering, the finite settling of the reference voltage during the SAR conversion, and the modified DAC switching scheme to reduce the DAC switching energy. © 2014 IEEE.