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Baik J.-W.,Broadcasting and Telecommunications Convergence Research Laboratory | Lee T.-H.,Korea University | Pyo S.,Korea University | Han S.-M.,Soonchunhyang University | And 2 more authors.
IEEE Transactions on Antennas and Propagation | Year: 2011

A novel printed crossed dipole with broad axial ratio (AR) bandwidth is proposed. The proposed dipole consists of two dipoles crossed through a 90° phase delay line, which produces one minimum AR point due to the sequentially rotated configuration and four parasitic loops, which generate one additional minimum AR point. By combining these two minimum AR points, the proposed dipole achieves a broadband circularly polarized (CP) performance. The proposed antenna has not only a broad 3 dB AR bandwidth of 28.6% (0.75 GHz, 2.253.0 GHz) with respect to the CP center frequency 2.625 GHz, but also a broad impedance bandwidth for a voltage standing wave ratio (VSWR) ≤q2 of 38.2% (0.93 GHz, 1.972.9 GHz) centered at 2.435 GHz and a peak CP gain of 8.34 dBic. Its arrays of 1 × 2 and 2 × 2 arrangement yield 3 dB AR bandwidths of 50.7% (1.36 GHz, 23.36 GHz) with respect to the CP center frequency, 2.68 GHz, and 56.4% (1.53 GHz, 1.953.48 GHz) at the CP center frequency, 2.715 GHz, respectively. This paper deals with the designs and experimental results of the proposed crossed dipole with parasitic loop resonators and its arrays. © 2006 IEEE. Source


Cho S.-I.,Broadcasting and Telecommunications Convergence Research Laboratory | Kang K.-M.,Broadcasting and Telecommunications Convergence Research Laboratory
ETRI Journal | Year: 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultrawideband systems. The proposed 128-point FFT processor employs both a modified radix-24 algorithm and a radix-23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 μm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures. © 2010 ETRI. Source


Chung T.J.,Broadcasting and Telecommunications Convergence Research Laboratory | Lee W.-H.,Broadcasting and Telecommunications Convergence Research Laboratory
ETRI Journal | Year: 2011

A 1.485-Gbit/s video signal transmission system at carrier frequencies of 240 GHz and 300 GHz was implemented and demonstrated. The radio frequency front-ends are composed of Schottky barrier diode subharmonic mixers (SHMs), frequency triplers, and diagonal horn antennas for the transmitter and receiver. Amplitude shift keying with an intermediate frequency of 5.94 GHz was utilized as the modulation scheme. A 1.485-Gbit/s video signal with a high-definition serial digital interface format was successfully transmitted over a wireless link distance of 4.2 m and displayed on an HDTV with a transmitted average output power of 20 μW at a 300-GHz system. © 2011 ETRI. Source


Park S.I.,Broadcasting and Telecommunications Convergence Research Laboratory | Kim H.M.,Broadcasting and Telecommunications Convergence Research Laboratory | Oh W.,Chungnam National University | Kim J.,Korea University
ETRI Journal | Year: 2012

In Advanced Television Systems Committee (ATSC) terrestrial digital television (DTV) systems, additional very low-rate data can be transmitted by modulating the amplitude and polarity of the transmitter identification (TxID) signal. Although the additional data transmission scheme offers reliable transmission and has a very large coverage area, it has a limitation on the data rate. In this paper, we propose a novel additional data transmission scheme based on the TxID sequences of the ATSC DTV system and Walsh modulation. The proposed scheme not only increases the data rate significantly, but also offers a virtually identical coverage area compared to a conventional scheme. © 2012 ETRI. Source


Kang M.-S.,Broadcasting and Telecommunications Convergence Research Laboratory | Kim B.-S.,Broadcasting and Telecommunications Convergence Research Laboratory | Kim K.S.,Broadcasting and Telecommunications Convergence Research Laboratory | Byun W.-J.,Broadcasting and Telecommunications Convergence Research Laboratory | Park H.C.,Seoul National University of Science and Technology
ETRI Journal | Year: 2012

This paper presents a novel 16-quadrature-amplitude- modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a 0.1 μm gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10-5 at a signal-to-noise ratio of about 21.5 dB. © 2012 ETRI. Source

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