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Haxton T.K.,Lawrence Berkeley National Laboratory | Zhou H.,Columbia University | Zhou H.,Brion Technologies | Tamblyn I.,Lawrence Berkeley National Laboratory | And 7 more authors.
Physical Review Letters | Year: 2013

Controlling the self-assembly of surface-adsorbed molecules into nanostructures requires understanding physical mechanisms that act across multiple length and time scales. By combining scanning tunneling microscopy with hierarchical ab initio and statistical mechanical modeling of 1,4-substituted benzenediamine (BDA) molecules adsorbed on a gold (111) surface, we demonstrate that apparently simple nanostructures are selected by a subtle competition of thermodynamics and dynamics. Of the collection of possible BDA nanostructures mechanically stabilized by hydrogen bonding, the interplay of intermolecular forces, surface modulation, and assembly dynamics select at low temperature a particular subset: low free energy oriented linear chains of monomers and high free energy branched chains. © 2013 American Physical Society.


Cohen J.G.,California Institute of Technology | Huang W.,Brion Technologies | Kirby E.N.,California Institute of Technology
Astrophysical Journal | Year: 2011

NGC2419 is a massive outer halo Galactic globular cluster (GC) whose stars have previously been shown to have somewhat peculiar abundance patterns. We have observed seven luminous giants that are members of NGC2419 with Keck/HIRES at reasonable signal-to-noise ratio. One of these giants is very peculiar, with an extremely low [Mg/Fe] and high [K/Fe] but normal abundances of most other elements. The abundance pattern does not match the nucleosynthetic yields of any supernova model. The other six stars show abundance ratios typical of inner halo Galactic GCs, represented here by a sample of giants in the nearby GC M30. Although our measurements show that NGC2419 is unusual in some respects, its bulk properties do not provide compelling evidence for a difference between inner and outer halo GCs. © 2011. The American Astronomical Society. All rights reserved.


Liu P.,Brion Technologies
ECS Transactions | Year: 2013

Full-chip computational lithography is an important technology that enables low-k1 patterning. Examples of its applications include optical proximity correction (OPC), source-mask optimization (SMO) and verifications. In these applications, lithography models are required to predict the printed patterns on the wafer. Therefore the model accuracy has a direct impact to the quality of the final result. Rigorous physical models are accurate but computationally expensive. Therefore simple approximate models are generally used in full-chip applications. As the k1-factor continues to shrink, the errors produced by these simple models become unacceptable. Advanced models with improved accuracy and reasonable speed are required for low-k1 applications. In this work we will discuss the issues with the existing full-chip models and the development of advanced models. Copyright © 2013 by ECS - The Electrochemical Society.


Liu P.,Brion Technologies
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

Best focus variation among different device features is one of the limiting factors to process window in semiconductor photolithography applications. Accurate prediction of best focus variation in full-chip optical proximity correction (OPC) and verifications is important in order to detect and mitigate the problem in design and post-design stages. In this work, the origin of best focus variation is first studied analytically by analyzing a simple but important imaging problem. It shows that phase difference between diffraction orders causes best focus shift. Then a rigorous simulation of mask diffraction further shows that the phase difference induced by 3D mask topography is non-zero and is a function of pattern and angle of incidence onto the mask. As a result, 3D mask models that can take into account oblique incidence effects are required in order to accurately predict best focus variations in full-chip applications. Tachyon M3D is a fast 3D mask model developed for full-chip OPC and verifications. Its accuracy in predicting best focus variation against measured wafer data is evaluated in this work. The results show very good correlation between M3D simulations and experiments. © 2011 SPIE.


Liu P.,Brion Technologies | Zhang Z.,Brion Technologies | Lan S.,Brion Technologies | Zhao Q.,Brion Technologies | And 4 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2012

3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography, resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the importance and modeling requirements for accurate prediction of best focus variations among different device features induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model, Tachyon W3D, and the preliminary results against rigorous simulations. © 2012 SPIE.


Finders J.,ASML Inc | Dusa M.,ASML Inc | Mulkens J.,ASML Inc | Cao Y.,Brion Technologies | Escalante M.,ASML Inc
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

ArF immersion lithography will be the main candidate for lithography patterning at the 22nm node. For both logic and memory type applications, double patterning techniques have to be applied to reach design pitches well below 70nm. In the lithography this combines aggressive imaging at low k1 (0.28... 0.31) and aggressive absolute CDU requirements (approximately 6-10% of nominal CD) of 1.5..2nm 3σ. We will look into the lithography requirements to achieve such aggressive CDU numbers and will discuss solutions for achieving the required level of intra-field, inter-field, waferto- wafer and scanner-to-scanner CD variations. © 2011 SPIE.


Takigawa T.,Brion Technologies | Gronlund K.,Brion Technologies | Wiley J.,Brion Technologies
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

Wafer lithography process windows can be enlarged by using source mask co-optimization (SMO). Recently, SMO including freeform wafer scanner illumination sources has been developed. Freeform sources are generated by a programmable illumination system using a micro-mirror array or by custom Diffractive Optical Elements (DOE). The combination of freeform sources and complex masks generated by SMO show increased wafer lithography process window and reduced MEEF. Full-chip mask optimization using source optimized by SMO can generate complex masks with small variable feature size sub-resolution assist features (SRAF). These complex masks create challenges for accurate mask pattern writing and low false-defect inspection. The accuracy of the small variable-sized mask SRAF patterns is degraded by short range mask process proximity effects. To address the accuracy needed for these complex masks, we developed a highly accurate mask process correction (MPC) capability. It is also difficult to achieve low false-defect inspections of complex masks with conventional mask defect inspection systems. A printability check system, Mask Lithography Manufacturability Check (M-LMC), is developed and integrated with 199-nm high NA inspection system, NPI. M-LMC successfully identifies printable defects from all of the masses of raw defect images collected during the inspection of a complex mask. Long range mask CD uniformity errors are compensated by scanner dose control. A mask CD uniformity error map obtained by mask metrology system is used as input data to the scanner. Using this method, wafer CD uniformity is improved. As reviewed above, mask-litho integration technology with computational lithography is becoming increasingly important. © 2010 SPIE .


Liu P.,Brion Technologies | Xie X.,Brion Technologies | Liu W.,Brion Technologies | Gronlund K.,Brion Technologies
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2013

Extreme ultraviolet lithography (EUVL) uses a 13.5nm exposure wavelength, all-reflective projection optics, and a reflective mask under an oblique illumination with a chief ray angle of about 6 degrees to print device patterns. This imaging configuration leads to many challenges related to 3D mask topography. In order to accurately predict and correct these problems, it is important to use a 3D mask model in full-chip EUVL applications such as optical proximity correction (OPC) and verifications. In this work, a fast approximate 3D mask model developed previously for full-chip deep ultraviolet (DUV) applications is extended and greatly enhanced for EUV applications and its accuracy is evaluated against a rigorous 3D mask model. © 2013 SPIE.


News Article | December 19, 2006
Site: venturebeat.com

Dutch chip company ASML Holding NV said it will buy Santa Clara’s Brion Technologies, a semiconductor design and wafer manufacturing company for $270 million, resulting in what appears to be a solid return for Brion’s multiple venture investors. Brion’s computational lithography technology lets chip manufacturers “simulate the realized pattern of integrated circuits and to correct the mask pattern to optimize the manufacturing process and yield.” Founded in 2002, Brion raised close to $30 million from a group of investors, led by U.S. Venture Partners. JAFCO Ventures, JP Morgan, Mohr Davidow Ventures, Morgenthaler Ventures, Stanford University and WK Technology Fund also invested. The is the latest in a string of sales by U.S. Venture Partners of its portfolio companies.


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