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Shenzhen, China

Yu Z.,Fudan University | Xiao R.,Bosera Asset Management Co. | You K.,Marvell Technology Group | Quan H.,Parade Technologies | And 10 more authors.
IEEE Transactions on Circuits and Systems I: Regular Papers

A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 × 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm2 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator. © 2013 IEEE. Source

Liu J.,Central University of Finance and Economics | Wu W.,University of International Business and Economics | Xu J.,Central University of Finance and Economics | Zhao H.,Bosera Asset Management Co.
Journal of Systems Science and Complexity

This paper presents simple and fast algorithms for computing very tight upper and lower bounds on the prices of American Asian options in the binomial model. The authors choose two types sets of the actual arithmetic average prices, instead of the simulated values in other existing models, as the representative average prices at each node of the binomial tree. This approach simplifies effectively the computation and reduces the error caused by the linear interpolation. Numerical results show that the approach produces accurate upper and lower bounds compared to the other existing methods based on the binomial tree. © 2014, Institute of Systems Science, Academy of Mathematics and Systems Science, CAS and Springer-Verlag Berlin Heidelberg. Source

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