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Gambini S.,Berkeley Wireless Research Center | Crossley J.,University of California at Berkeley | Alon E.,University of California at Berkeley | Rabaey J.M.,University of California at Berkeley
IEEE Journal of Solid-State Circuits | Year: 2012

We present an ultra-wideband transceiver designed for ultra-low-power communication at sub-10 cm range. The transceiver operates at a 5.6 GHz carrier frequency, chosen to minimize path loss when using a 1 cm antenna, and can switch its architecture between self-synchronous rectification and low-IF to adapt its power consumption to the channel characteristic in real time. A low-power digital circuit exploits redundancy in the modulation scheme to provide a real-time BER estimate used to close the mode-switching loop. Implemented in 65 nm CMOS, the transceiver consumes 25 μ when transmitting and 245 μ when receiving in low-power mode, plus 45 μ in the clock generator, and only requires an external antenna. Dual-mode operation allows range extension and mitigates interference. © 2012 IEEE. Source


Niknejad A.M.,Berkeley Wireless Research Center
IEEE Microwave Magazine | Year: 2010

Silicon based 60 GHz is a promising technology for high data rate communication. The research team at IBM demonstrated full transceiver front-ends in a SiGe BiCMOS. Dual-conversion superheterodyne radio architecture was selected over a homodyne approach due to its lower carrier feed-through in the transmitter and better I/Q quadrature accuracy. The low-noise amplifier (LNA) is at the lower left and the spiral inductors in the receiver mixer and intermediate frequency (IF) variable gain amplifier (IF VGA) is visible to the right of the LNA. The frequency tripler is in the center, and the phase locked loop (PLL) occupies the right third of the chip. On-wafer measurements were made on the full receiver, including the PLL. The PLL occupies the right third of the chip, and the baseband-to-IF mixer contains the two spiral inductors at the top center. The PA is operated from a 1-V supply to improve reliability and has a simulated small signal gain of 14 dB at 60 GHz. CW measurements verify that the PA can deliver 111 dBm of saturated output power with a peak PAE of 14.6%. Source


Alioto M.,University of Siena | Alioto M.,Berkeley Wireless Research Center
2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 | Year: 2011

In this paper, the impact of the NMOS/PMOS imbalance on Ultra-Low Voltage (ULV) circuits and their design is discussed within a unitary framework for the first time. Variations are shown to dramatically affect imbalance due to the long-tailed probability density and high variability. The impact of the imbalance on the minimum supply voltage VDD,min ensuring correct gate switching is studied analytically. The results theoretically justify the experimental results in [1], which agree very well with the predictions. The impact of the imbalance on the leakage energy in VLSI systems is also analyzed through a simple but representative example. An analytical model is presented to predict such leakage energy increase due to imbalance. Extensive results in 65-nm CMOS are shown to agree with the design considerations and quantitative models presented. © 2011 IEEE. Source


Alioto M.,University of Siena | Alioto M.,Berkeley Wireless Research Center
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

In this paper, subthreshold static CMOS logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm CMOS technology. ©2010 IEEE. Source


Alioto M.,University of Siena | Alioto M.,Berkeley Wireless Research Center
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

In this paper, the layout density of three-terminal FinFET logic circuits is extensively analyzed. As opposite to previous works, which are focused either on single devices or simplistic circuits, this analysis explicitly includes the geometric constraints that are imposed by the standard cell approach. The impact of the fin technology is analyzed by comparing the lithography- and spacer-defined approaches, as well as evaluating the dependence of layout density on the fin height. Results show that FinFET standard cells have a layout density that is better than bulk cells even for moderately tall fins. The fin height is also shown to be a powerful knob to improve the layout density in FinFET cells. Analysis also shows that the usually claimed 2X density improvement of the spacer-defined technology compared to the lithographydefined is dramatically reduced in real standard cells, and can be negligible for tall fins. All results are justified through considerations at the physical level of abstraction. Various versions of a 32-nm 44-gate library are laid out to carry out the analysis. ©2010 IEEE. Source

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