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Liu L.B.,Tsinghua University | Chen Y.J.,Tsinghua University | Yin S.Y.,Tsinghua University | Zhou L.,CAS Institute of Microelectronics | And 2 more authors.
Science China Information Sciences | Year: 2014

In this paper, a TPP (Task-based Parallelization and Pipelining) scheme is proposed to implement AVS (Audio Video coding Standard) video decoding algorithm on REMUS (REconfigurable MUltimedia System), which is a coarse-grained reconfigurable multimedia system. An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning. Several parallel techniques, such as MB (Macro-Block)-based parallel and block-based parallel techniques, and several pipeline techniques, such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation, for performance improvement of the AVS decoder. Also, most computation-intensive tasks in AVS video standards, such as MC (Motion Compensation), IP (Intra Prediction), IDCT (Inverse Discrete Cosine Transform), REC (REConstruct) and DF (Deblocking Filter), are performed in the two RPUs (Reconfigurable Processing Units), which are the major computing engines of REMUS. Owing to the proposed scheme, the decoder introduced here can support AVS JP (Jizhun Profile) 1920×1088@39fps streams when exploiting a 200 MHz working frequency. © 2014 Science China Press and Springer-Verlag Berlin Heidelberg.

Liu L.B.,Tsinghua University | Chen Y.J.,Tsinghua University | Wang D.,Tsinghua University | Yin S.Y.,Tsinghua University | And 5 more authors.
Science China Information Sciences | Year: 2014

This paper proposes a task-based hybrid parallel and hybrid pipeline (THPHP) scheme to implement multi-standard video algorithms, including MPEG-2, H.264, and audio video coding standard (AVS), on a heterogeneous coarse-grained reconfigurable processor, called the reconfigurable multimedia system (REMUS). The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition (HD) video decoding standards. In THPHP, we propose both a task-based hybrid parallel scheme, in which macro-block (MB)-level, block-level, and sub-block-level decoding tasks are parallelized to improve data processing throughput, and a hybrid pipeline scheme, in which slice-level, MB-level, block-level and sub-block-level computations are pipelined to improve efficiency. Computation-intensive tasks, such as motion compensation, intra prediction, inverse discrete cosine transform, reconstruction, and deblocking filter, are implemented on two reconfigurable processing units, which are the core computing engines of REMUS. Thanks to the proposed schemes, the implementations can achieve H.264 high profile (HP) 1920×1080@30 fps streams, AVS Jizhun profile (JP) 1920×1080@39 fps streams, and MPEG-2 main profile (MP) 1920×1080@41 fps streams when working at 200 MHz frequency. Compared with XPP-III (a commercial reconfigurable processor), when implementing H.264 HD decoding, the performance and energy efficiency on REMUS are improved by 1.81× and 14.3×, respectively. © 2013 Science China Press and Springer-Verlag Berlin Heidelberg.

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