Palo Alto, CA, United States
Palo Alto, CA, United States
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Patent
Barefoot Networks | Date: 2015-09-24

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.


Patent
Barefoot Networks | Date: 2015-09-24

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.


Patent
Barefoot Networks | Date: 2015-08-26

A method for generating configuration data for configuring a hardware switch is described. The method receives a description of functionality for the hardware switch. Based on the description, the method generates sets of match and action entries to configure the hardware switch to process packets. The method then determines, for each packet header field in a parse graph that specifies instructions for a parser of the switch to extract packet header fields from packets, whether the packet header field is used or modified by at least one match or action entry. The method generates for the parser of the hardware switch configuration data that instructs the parser to extract (i) packet header fields used or modified by at least one match or action entry to a first set of registers and (ii) packet header fields not used by any match or action entries to a second set of registers.


Patent
Barefoot Networks | Date: 2015-08-26

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.


Patent
Barefoot Networks | Date: 2015-09-24

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.


Patent
Barefoot Networks | Date: 2015-08-26

The invention provides a packet loss detection system that in near-real time detects packet loss and reports the identities of the lost packets. The identities of the lost packets are based on a set of packet-specific information that includes five-tuple flow information of the packet and other unique packet identifiers. A set of meters are placed at various vantage points in the network, each meter generates digests summarizing all the traffic passing through itself. The digests are exported to a collector/analyzer, which decodes the digests and performs an analysis to detect packet losses and to determine the lost packets identities. The collector compares between the traffic digests generated by all the meters surrounding the segment. Mismatches among the digests indicate packet losses. The collector restores the identifiers of the lost packets by further decoding the mismatches between the digests.


Patent
Barefoot Networks | Date: 2015-08-21

The invention provides a packet loss detection system that in near-real time detects packet loss and reports the identities of the lost packets. The identities of the lost packets are based on a set of packet-specific information that includes five-tuple flow information of the packet and other unique packet identifiers. A set of meters are placed at various vantage points in the network, each meter generates digests summarizing all the traffic passing through itself. The digests are exported to a collector/analyzer, which decodes the digests and performs an analysis to detect packet losses and to determine the lost packets identities. The collector compares between the traffic digests generated by all the meters surrounding the segment. Mismatches among the digests indicate packet losses. The collector restores the identifiers of the lost packets by further decoding the mismatches between the digests.


Patent
Barefoot Networks | Date: 2016-01-27

A pool of unit memories is provided in order to flexibly allocate memory capacity to implement various tables and/or logical memories such as those for implementing an OpenFlow switch. The pool is structured with routing resources for allowing flexible allocation and reallocation of memory capacity to the various tables. The unit memories and logical units in the pool are interconnected by a set of horizontal routing resources and a set of vertical routing resources.


Patent
Barefoot Networks | Date: 2015-12-14

Some embodiments provide a method for configuring unit memories to implement first and second sets of entries, the second set of which references the first set. The method configures a first pool of memories to implement the first set. Each first-set entry is located at a particular location in at least one of the first-pool memories. The method configures a second pool of memories to implement the second set of entries. Each second-set entry includes (i) a first set of bits for indicating a memory page that corresponds to one or more first-pool memories, (ii) a second set of bits for specifying a location in each of the one or more memories from which to retrieve data for the referenced first-set entry, and (iii) a third set of bits for specifying a sub-location within the retrieved data. The number of bits in the third set of bits is fixed for the second-set entries while a number of sub-locations varies for different locations specified by the second set of bits of different second-set entries.


Patent
Barefoot Networks | Date: 2015-12-14

Some embodiments provide a method that configures a first pool of unit memories to implement several match entries, each including a set of match conditions. Each memory in the first pool includes at least one set of match entries. The method configures a second pool of unit memories to implement several action entries each located at a location in a memory. Each unit memory in the second pool has a different memory page address. The method assigns each set of match entries a virtual memory page address that corresponds to a different memory in the second pool. When the set of match conditions are met for a particular match entry at a particular location in a particular virtual memory page address, a particular action entry is read, having a same location in a memory with a same virtual memory page address in the second pool.

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