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Terrassa, Spain

Michalik P.,Polytechnic University of Catalonia | Fernandez D.,Baolab Microsystems | Madrenas J.,Polytechnic University of Catalonia
Electronics Letters | Year: 2012

A novel sampling scheme for coarse-fine time-to-digital converters (TDCs), whose architecture commonly comprises a synchronous counter as a coarse part and delay-line based phase interpolator as a fine part, is proposed. The presented approach eliminates any error in the coarse counter and is superior in terms of mean time between failures as well as complexity, area and power consumption in comparison to previously reported solutions. © 2012 The Institution of Engineering and Technology.


Patent
Baolab Microsystems | Date: 2010-05-20

A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.


A method for manufacturing an integrated circuit including producing layers that form one or more electrical and/or electronic elements on a semiconductor material substrate. Then, producing ILD layers above the layers forming one or more electrical and/or electronic elements, including the steps of depositing a first layer of etch stopper material, depositing a second layer of dielectric material above and in contact with the first layer, forming at least one track extending through the first and second layers, and filling the at least one track with a non-metallic material.


Patent
Baolab Microsystems | Date: 2012-02-01

Systems and methods for manufacturing a chip comprising a plurality of MEMS devices arranged in an integrated circuit are provided. In one aspect, the systems and methods provide for a chip including electronic elements formed on a semiconductor material substrate. The chip further includes a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. MEMS devices are formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers. The stack of interconnection layers includes at least one unetched layer of dielectric material, and at least one layer of conductor material for routing connections to and from the electronic elements.


Patent
Baolab Microsystems | Date: 2013-11-13

A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.

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