Magdeburg-rothensee, Germany
Magdeburg-rothensee, Germany

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A layer structure 100 for a surface-emitting LED having an emission surface 101 that is closer to a p-side of the structure than to an n-side of the structure, and further comprising a transparent anode layer 110, a p-type layer 120, a light-emitting group-III-nitride structure 130, an n-type layer 140, a cathode layer 150, an electrically insulating layer 160 under the cathode layer, a metallically conductive anode contact substrate 170 under the insulating layer, at least one vertical interconnect 175 electrically connecting the anode contact substrate and the anode layer, a metallically conductive cathode contact substrate 180 electrically connected with and arranged under the cathode layer, wherein either the insulating layer or the cathode layer is reflective, and wherein the cathode contact substrate and/or the anode contact substrate have a suitable thickness for forming a mechanical support of the layer structure.


Patent
AZZURRO Semiconductors | Date: 2011-12-23

A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate, the layer sequence comprising at least one doped first group-III-nitride layer (105) having a dopant concentration larger than 110^(18 )cm^(3), a second group-III-nitride layer (106) having a thickness of at least 50 nm and an n-type or p-type dopant concentration of less than 510^(18 )cm^(3), and an active region made of a group-III-nitride semiconductor material, wherein the first group-III-nitride layer comprises at least one n-type dopant selected from the group of elements formed by germanium, tin, lead, oxygen, sulphur, selenium and tellurium or a at least one p-type dopant, and wherein the active region has a volume density of either screw-type or edge type dislocations below 510^(9 )mm^(3).


Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.


Patent
AZZURRO Semiconductors | Date: 2012-03-02

A semiconductor light emitter device for emitting light having a photon energy, comprises a mechanical carrier made substantially of a material that is an absorbant of the light with the photon energy, and having a carrier bottom side and a carrier top side opposite to the carrier bottom side, a layer structure epitaxially deposited on the carrier bottom side of the mechanical carrier and comprising an active-layer stack with at least two semiconductor layers of opposite conductivity types, which is configured to emit light upon application of a voltage to the active-layer stack, and at least one opening in the mechanical carrier, the opening reaching from the carrier bottom side to the carrier top side and being arranged and shaped to allow a passage of light, which is emitted from the active-layer stack, through the opening in the mechanical carrier.


Patent
AZZURRO Semiconductors | Date: 2014-11-05

A layer sequence (100) for use in fabricating an electronic device, the layer sequence (100) comprising a substrate (110); a buffer layer on the substrate; a channel layer (130) made of a first group-III-nitride semiconductor material on the buffer layer structure (120); a barrier layer (150) arranged on the channel layer (130) and exhibiting a larger band-gap than the channel layer (130) on its barrier-layer side that faces the channel layer (130), allowing a formation of a two-dimensional electron gas near an interface between the channel layer (130) and the barrier layer (150); wherein the barrier layer (150) is formed by a barrier layer sequence, which comprises at least three group-III-nitride barrier-sublayers (150.1, 150.2, 150.3), of which first barrier-sublayers (105.1) having a first band-gap and second barrier-sublayers (150.2) having a second band-gap smaller than the first band gap are arranged in an alternating manner in the barrier layer sequence.


An epitaxial wafer 100, comprising a silicon substrate having a principal surface with a center region 110 and an edge region near an outer circumferential line of the principal surface, and a polycrystalline or amorphous edge-mask layer 120, which is made of a material suitable for growth of group-III-nitride material thereon and which is deposited directly and only on the edge region of the principal surface, such that the center region 110 and the edge-mask layer 120 together form a growth substrate for a group-III-nitride buffer layer 130 structure conformally deposited thereon.


Patent
AZZURRO Semiconductors | Date: 2012-09-05

A semiconductor light emitter device for emitting light having a photon energy, comprises- a mechanical carrier made substantially of a material that is an absorbant of the light with the photon energy, and having a carrier bottom side and a carrier top side opposite to the carrier bottom side;- a layer structure epitaxially deposited on the carrier bottom side of the mechanical carrier and comprising an active-layer stack with at least two semiconductor layers of opposite conductivity types, which is configured to emit light upon application of a voltage to the active-layer stack; and- at least one opening in the mechanical carrier, the opening reaching from the carrier bottom side to the carrier top side and being arranged and shaped to allow a passage of light, which is emitted from the active-layer stack, through the opening in the mechanical carrier.


Patent
AZZURRO Semiconductors | Date: 2014-08-20

A layer structure (100) for a normally-off transistor comprises an electron-supply layer (910) made of a group-III-nitride material, a back-barrier layer (906) made a group-III-nitride material, a channel layer (908) between the electron-supply layer (910) and the back-barrier layer (906), made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer (906) is of p-type conductivity, while the material of the electron-supply layer (910) and the material of the channel layer (908) are not of p-type conductivity, the band-gap energy of the electron-supply layer (910) is smaller than the band-gap energy of the back-barrier layer (906); in absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer (908) is higher in energy than a Fermi level of the material in the channel layer (908).


Patent
AZZURRO Semiconductors | Date: 2014-08-20

The invention relates to an epitaxial group-III-nitride buffer-layer structure (100) on a heterosubstrate, wherein the buffer-layer structure (100) comprises at least one stress-management layer sequence S including an interlayer structure (530) arranged between and adjacent to a first and a second group-III-nitride layer (120, 140), wherein the interlayer structure (130) comprises a group-III-nitride interlayer material having a larger band gap than the materials of the first and second group-III-nitride layers (120, 140), and wherein a p-type-dopant-concentration profile drops, starting from at least 1x10^(18) cm^(-3), by at least a factor of two in transition from the interlayer structure (130) to the first and second group-III-nitride layers (120, 140).

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