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San Jose, CA, United States

Patent
Avogy Inc | Date: 2015-07-31

A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.


Grant
Agency: Department of Energy | Branch: ARPA-E | Program: SBIR | Phase: Phase II | Award Amount: 1.50M | Year: 2014

In this abstract the development of vertical power transistors utilizing bulk GaN substrates with breakdown voltages of 1200V or higher, normally-off operation, and a drain current rating of 100A is proposed. These devices will feature vertical current flow, avalanche ruggedness, and a wide operating temperature range (-55 to 150°C). The target specific on-resistance for the transistor is 30x lower than the best-in-class Si MOSFETs and its switching frequency more than 10x faster than state-of-the art IGBTs. Cost parity with silicon devices will be achieved in three years using a two prong approach. Firstly, the bulk GaN substrate price will be reduced by: (i) using a scalable ammonothermal substrate technology, (ii) enabling commercially available substrates obtained from the epitaxial lift-off process, and (iii) driving the price of GaN substrates down along with the solid-state LED lighting industry. Secondly, manufacturing cost will be reduced by predominantly using legacy silicon fabrication equipment in the Avogy facility in San Jose, CA. The transistor and technology performance metrics will be verified by an independent testing facility. Also, in this proposal gate drivers will be developed for these vertical transistors to replace existing MOSFETs and IGBTs. Finally, commercialization partners will evaluate devices and gate drives in power conversion applications.


A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.


Patent
Avogy Inc | Date: 2015-10-26

A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.


A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 m thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.

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