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A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.


Patent
Avalanche Technology | Date: 2016-06-06

The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure in between a seed layer and a cap layer. The MTJ structure includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by an intermediate magnetic reference layer. The first, second, and intermediate magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction that is opposite to the first invariable magnetization direction.


Patent
Avalanche Technology | Date: 2016-07-06

A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.


The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.


Patent
Avalanche Technology | Date: 2016-03-24

The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer.


Patent
Avalanche Technology | Date: 2016-02-26

The present invention is directed to an MTJ memory element including a magnetic free layer structure which comprises one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic coupling layer opposite the second magnetic reference layer.


The present invention is directed to a spin transfer torque magnetic random access memory (STTMRAM) element comprising a composite free layer including one or more stacks of a bilayer unit that comprises an insulator layer and a magnetic layer with the magnetic layer having a variable magnetization direction substantially perpendicular to a layer plane thereof; a magnetic pinned layer having a first fixed magnetization direction substantially perpendicular to a layer plane thereof; a tunnel barrier layer formed between the composite free layer and the magnetic pinned layer; and a magnetic fixed layer coupled to the magnetic pinned layer through an anti-ferromagnetic coupling layer. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to a layer plane thereof and is substantially opposite to the first fixed magnetization direction.


A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.


Patent
Avalanche Technology | Date: 2016-05-06

The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.


A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

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