Fremont, CA, United States
Fremont, CA, United States

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Patent
Avalanche Technology | Date: 2017-01-20

The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.


Patent
Avalanche Technology | Date: 2017-01-26

A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.


A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.


Patent
Avalanche Technology | Date: 2017-02-23

The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure that comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a first perpendicular enhancement layer (PEL) formed adjacent to the magnetic free layer structure; a magnetic dead layer formed adjacent to the first PEL; and a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a second PEL. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.


Patent
Avalanche Technology | Date: 2016-01-29

The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.


Patent
Avalanche Technology | Date: 2016-06-06

The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure in between a seed layer and a cap layer. The MTJ structure includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by an intermediate magnetic reference layer. The first, second, and intermediate magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction that is opposite to the first invariable magnetization direction.


Patent
Avalanche Technology | Date: 2016-03-24

The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer.


A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.


Patent
Avalanche Technology | Date: 2016-05-06

The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.


A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

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