Munich, Germany
Munich, Germany

Avago Technologies is a designer, developer and supplier of analog, digital, mixed signal and optoelectronics components and subsystems. Hock Tan is the company's president and CEO. Avago Technologies is jointly headquartered in San Jose, California and Singapore. Wikipedia.


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Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.


Patent
Avago Technologies | Date: 2016-07-29

A compact bidirectional optical transceiver module is provided that has a bidirectional optical subassembly (BOSA) that includes a stamped metal optic that folds the optical pathway, alignment features that enable the optoelectronic components of the electrical subassembly (ESA) to be precisely aligned with the BOSA in all dimensions, and features that reduce the capacitance of the driver circuitry to improve signal integrity and widen the eye opening.


Patent
Avago Technologies | Date: 2016-03-01

A method of a storage area network (SAN) includes storing and communicating data received from a server at a host bus adapter via a bus controller of the adapter. In a case where the data is associated with an address corresponding to a default boot logical unit (LUN) of a non-volatile memory (NVM) of the adapter, the data is stored in the NVM. In a case where the data is not associated with an address corresponding to a boot LUN of the NVM, the data is communicated over the SAN. During power up of the adapter, in a case where it is determined that the NVM includes an image of an operating system, the adapter uses the bus controller to provide the server with information to select the NVM as a boot LUN for booting the operating system.


Patent
Avago Technologies | Date: 2016-01-29

There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.


A bulk acoustic wave (BAW) resonator device includes a bottom electrode on a substrate over one of a cavity and an acoustic mirror, a piezoelectric layer on the bottom electrode, a top electrode on the piezoelectric layer, and a temperature compensation feature having positive temperature coefficient for offsetting at least a portion of a negative temperature coefficient of the piezoelectric layer. At least one of the bottom electrode and the top electrode includes an integrated lateral feature configured to create at least one of a cut-off frequency mismatch and an acoustic impedance mismatch.


Patent
Avago Technologies | Date: 2016-06-29

An acoustic resonator device includes a bottom electrode disposed on a substrate over an air cavity, a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer, where an overlap between the top electrode, the piezoelectric layer and the bottom electrode over the air cavity defines a main membrane region. The acoustic resonator device further includes at least one metal frame disposed on a bottom surface of the bottom electrode having a thickness that ranges from about 10% to about 75% of a thickness of the bottom electrode in a central region of the bottom electrode. The thickness of the metal frame improves heat dissipation out of the acoustic resonator device while also improving structural stability of the acoustic resonator device without detrimentally affecting its performance.


Patent
Avago Technologies | Date: 2016-02-09

A computing or controlling apparatus includes a remote direct memory access (RDMA) adapter device. Responsive to an initialized state, a create queue pair adapter device command is provided by a host processing unit. The adapter device processes the command to create a queue pair in the initialized state. Responsive to a ready to send (RTS) state, a queue pair state transition command is provided by the host processing unit. The adapter device processes the queue pair state transition command to transition the queue pair from the initialized state to the ready to send (RTS) state skipping over the ready to receive (RTR) state. However, if the adapter device processes a ready to receive (RTR) in-band RDMA WQE received from the host processing unit, the state of the queue pair transitions from the initialized state to the RTR state. The adapter device then processes a ready to send (RTS) in-band RDMA WQE received from the host processing unit via the queue pair to transition the queue pair from the RTR state to the RTS state.


Patent
Avago Technologies | Date: 2016-01-15

Tunneling packets of one or more remote direct memory access (RDMA) unreliable queue pairs of a first adapter device through an RDMA reliable connection (RC) by using RDMA reliable queue context and RDMA unreliable queue context stored in the first adapter device. The RDMA reliable connection is initiated between a first RDMA RC queue pair of the first adapter device and a second RDMA RC queue pair of a second adapter device. The RDMA reliable queue context is for the first RDMA RC queue pair, and the RDMA unreliable queue context is for the one or more RDMA unreliable queue pairs of the first adapter device.


Patent
Avago Technologies | Date: 2016-07-27

A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.


Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.

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