Munich, Germany
Munich, Germany

Avago Technologies is a designer, developer and supplier of analog, digital, mixed signal and optoelectronics components and subsystems. Hock Tan is the company's president and CEO. Avago Technologies is jointly headquartered in San Jose, California and Singapore. Wikipedia.


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Patent
Avago Technologies | Date: 2016-08-04

An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.


Patent
Avago Technologies | Date: 2017-01-05

An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.


Patent
Avago Technologies | Date: 2016-11-01

A device includes circuitry configured to determine one or more signal processing capabilities of another device in communication with the device. The device configures a signal compression mode of the device to correspond to a first signal compression mode of a plurality signal compression modes based on the one or more signal processing capabilities of the other device. The device s configured to modify, in response to detecting variations in one or more network configuration properties or the one or more signal processing capabilities of the other device, the signal compression mode of the device.


Patent
Avago Technologies | Date: 2015-11-23

An apparatus includes a storage medium operable to store a number of data tracks, a read channel circuit operable to process the data tracks read from the storage medium, and a track quality classifier circuit operable to determine a track quality metric for the data tracks read from the storage medium. The track quality metric indicates whether a corresponding one of the data tracks that has failed to successfully process in the read channel circuit can be reprocessed within a track gap period.


An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a parity check matrix with non-uniform column weights, and at least one scaling circuit configured to scale values in the data decoding circuit with a scaling value that is dependent at least in part on a column weight of the likelihood values being scaled.


Patent
Avago Technologies | Date: 2015-11-23

An apparatus for processing data includes a data detector configured to detect data values in data sectors to yield detected data, a data decoder configured to decode the detected data, wherein the data detector and the data decoder are configured to process the data sectors in a series of global iterations, a memory configured to store parity sector soft information, and a scheduler configured to control overlapping reprocessing of a failed sector in the data detector and the data decoder based on the parity sector soft information with processing of another data sector in the data detector and the data decoder.


A surface acoustic wave (SAW) resonator structure includes a substrate, a piezoelectric layer disposed on the substrate, and an interdigital transducer (IDT) electrode disposed over the piezoelectric layer. The IDT electrode includes multiple busbars and multiple electrode fingers extending from each busbar, where the electrode fingers are configured to generate surface acoustic waves in the piezoelectric layer. The SAW resonator structure further includes dielectric material disposed between the piezoelectric layer and at least at portion of the IDT. The dielectric material may be positioned below tips of the electrode fingers, thereby mass-loading the electrode fingers.


Patent
Avago Technologies | Date: 2016-01-29

There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.


A bulk acoustic wave (BAW) resonator device includes a bottom electrode on a substrate over one of a cavity and an acoustic mirror, a piezoelectric layer on the bottom electrode, a top electrode on the piezoelectric layer, and a temperature compensation feature having positive temperature coefficient for offsetting at least a portion of a negative temperature coefficient of the piezoelectric layer. At least one of the bottom electrode and the top electrode includes an integrated lateral feature configured to create at least one of a cut-off frequency mismatch and an acoustic impedance mismatch.


Patent
Avago Technologies | Date: 2016-07-27

A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.

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