Graz, Austria

Austriamicrosystems AG

www.ams.com
Graz, Austria

ams AG, formerly known as austriamicrosystems AG and still known as AMS , is a multinational semiconductor manufacturer. The headquarters are located in Unterpremstätten . The main fields of the business are the development and production of high performance analog Integrated Circuitry such as standard analog products as well as customer specific solutions .ams AG is engaged in the areas of sensors and sensor interfaces, power management, and wireless. With their products they serve the markets of communication & consumer electronics, Industry|industrial & medical electronics and automotive electronics. The almost 1,400 employees in 20 countries include research and development facilities in Austria, a center of excellence in optical sensors in Texas , seven other design centers, and manufacturing in Austria and the Philippines. Wikipedia.

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Patent
Austriamicrosystems AG | Date: 2013-08-21

Disclosed is a Radio Frequency Identification (RFID) reader, a network and a method for communication in an RFID network. The RFID reader is adapted to operate in either a reader mode or in a tag emulation mode, wherein in the reader mode the RFID reader communicates with at least one RFID tag to access the tags memory contents, and in the tag emulation mode the RFID reader communicates with at least one other RFID reader to share memory content with the other RFID reader. Furthermore, an RFID network and a method for communication in an RFID network are described.


Patent
Austriamicrosystems AG | Date: 2013-05-01

A touch sensing system comprises a signal generator (Tx), which is configured to provide an AC signal, a signal receiver (Rx), which is configured to perform a signal detection, a first transmitter node (T1), which is connected to the signal generator (Tx) in a switchable fashion, a second transmitter node (T2), which is connected to the first transmitter node (T1) in a switchable fashion and to a reference potential terminal (GND) in a switchable fashion, a first receiver node (R1), which is connected to the signal receiver (Rx) in a switchable fashion and to the first transmitter node (T1) in a switchable fashion, a second receiver node (R2), which is connected to the first receiver node (R1) in a switchable fashion and to the reference potential terminal (GND) in a switchable fashion, a first electrode (E1), which is connected to the second transmitter node (T2) in a switchable fashion, a second electrode (E2), which is connected to the second receiver node (R2) in a switchable fashion, and a capacitance measurement circuit (CMC). The capacitance measurement circuit (CMC) is coupled to the first transmitter node (T1) and/or the second transmitter node (T2), coupled to the first receiver node (R1) and/or the second receiver node (R2), and configured to measure respective capacitance values at the first transmitter node (T1) or the second transmitter node (T2) and at the first receiver node (R1) or the second receiver node (R2 ) .


The semiconductor device comprises a substrate (1) of semiconductor material with a main surface (11) and an opposite surface (12), an integrated circuit component (2) in the substrate at or near the main surface, a structured metal plane (3) at a distance from the substrate above the main surface, a dielectric layer (4) between the metal plane and the substrate, an electrical interconnect (5) between the metal plane and the integrated circuit component, the interconnect traversing the dielectric layer, and an interconnection via (6) comprising a metallization (7) leading through the substrate between the main surface and the opposite surface. The metallization is connected to the metal plane via a further electrical interconnect (8) traversing the dielectric layer.


Patent
Austriamicrosystems AG | Date: 2013-09-11

A semiconductor substrate (1) is provided with a source region (2) and a drain region (3) of a first type of electrical conductivity arranged at a surface (10) at a distance from one another, a channel region (4) of a second type of electrical conductivity, which is opposite to the first type of electrical conductivity, arranged between the source region (2) and the drain region (3), and a gate electrode (6) arranged above the channel region (4). A substrate well (7) of the first type of electrical conductivity is arranged in the substrate (1) at a distance from the source region (2). The substrate well (7) is contiguous with the drain region (3), and the distance between the source region (2) and the substrate well (7) is larger than the distance between the source region (2) and the drain region (3).


Patent
Austriamicrosystems AG | Date: 2015-11-05

A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output to provide an amplified sensor signal, and a feedback path that couples the signal output to the signal input and provides a feedback current that is an attenuated signal of the amplified sensor signal and is inverted with respect to the sensor signal.


Patent
Austriamicrosystems AG | Date: 2013-12-18

A sensor arrangement (10) comprises an amplifier (11) having a signal input (12) to receive an input signal (SIN) and a signal output (13) to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement (10) comprises a series connection of a capacitive sensor (14) and a feedback capacitor (15), wherein the series connection couples the signal output (13) to the signal input (12). A voltage source arrangement (19) of the sensor arrangement (10) is connected to a feedback node (18) between the capacitive sensor (14) and the feedback capacitor (15).


Patent
Austriamicrosystems AG | Date: 2013-11-20

A first well (2) of a first type of conductivity is formed in a substrate (1). A second well (3) of an opposite type of conductivity is formed in the first well. A source region (4) is formed in the first well outside the second well. A drain region (5) is formed in the second well, leaving a drift region (13) in the second well between the drain region and the source region. A bulk contact region (6) is formed in the first well. A gate dielectric (8) and a gate electrode (9) are arranged on the substrate between the second well and the source region. The doping of the second well is reduced in the drift region by using an implantation mask (10) with a patterned window (11) comprising openings (12) that are confined in directions both along the drift region and transverse to the drift region.


Patent
Austriamicrosystems AG | Date: 2013-05-15

A lateral avalanche device comprises a semiconductor substrate (1) having a trench (4) with side walls (5) extending from a main surface (2) to a rear surface (3). A first doped region (11) is present at the side walls of the trench, and a second doped region (12) is arranged at a distance from the first doped region. A third doped region (13) is located adjacent to the first doped region, extends through the substrate from the main surface to the rear surface, and is arranged between the first doped region and the second doped region. The third doped region (13) is the avalanche multiplication region of the photodiode structure. The second doped region and the third doped region have a first type of conductivity, and the first doped region has a second type of conductivity which is opposite to the first type of conductivity. The region of the substrate that is between the first doped region and the second doped region is of the first type of conductivity.


Patent
Austriamicrosystems AG | Date: 2013-11-06

An electric circuit arrangement for galvanic isolated communication comprises a transmitter circuit (120) having an input side (E120) for applying a digital signal (PWM) and an output side (A120) for generating an output signal (AS) in dependence on the digital signal (PWM). The circuit arrangement further comprises a receiver circuit (220) having an input side (E220) for receiving an input signal (ES) and having an output side (A220) for generating a reconstructed digital signal (PWM) in dependence on the input signal (ES), and a transformer (210) for inductive coupling the output side (A120) of the transmitter circuit (120) to the input side (E220) of the receiver circuit (220).


A host device (10) may comprise an electrical power transmitting controller device (100), and an accessory device (20) may comprise an electrical power receiving controller device (200). After an identification and handshaking process to determine power requirements the power transmitting controller device (100) provides electrical power to the electrical power receiving controller device (200) to operate the accessory device. Coded communication data is transferred between the host device (10) and the accessory device (20) by a communication link. Power and communication are transferred over a single wire, such as an auxiliary pole (AUX) of a 3.5 mm jack interface (1020).

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