Cleveland, OH, United States
Cleveland, OH, United States

Time filter

Source Type

Park H.,Cornell University | Kim S.,Cornell University | Morris K.,Cornell University | Moukperian M.,Cornell University | And 2 more authors.
Applied Ergonomics | Year: 2015

The biomechanical experiment with eight male and four female firefighters demonstrates that the effect of adding essential equipment: turnout ensemble, self-contained breathing apparatus, and boots (leather and rubber boots), significantly restricts foot pronation. This finding is supported by a decrease in anterior-posterior and medial-lateral excursion of center of plantar pressure (COP) trajectory during walking. The accumulation of this equipment decreases COP velocity and increases foot-ground contact time and stride time, indicating increased gait instability. An increase in the flexing resistance of the boots is the major contributor to restricted foot pronation and gait instability as evidenced by the greater decrease in excursion of COP in leather boots (greater flexing resistance) than in rubber boots (lower resistance). The leather boots also shows the greatest increase in foot contact time and stride time. These negative impacts can increase musculoskeletal injuries in unfavorable fire ground environments. © 2014 Elsevier Ltd and The Ergonomics Society.

Palesko C.,SavanSys Solutions LLC | Palesko A.,SavanSys Solutions LLC | Vardaman E.J.,Austin International Inc.
Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014 | Year: 2014

As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. However, care must be taken to manage the total cost and yield of the system. Both of these technologies have the potential to meet the smaller and faster market requirement, but if either is used on the wrong design, the cost can be high and the yield can be low. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity costs and yields will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs. An in depth analysis of the cost of cumulative yield loss will be presented for both technologies. A sensitivity analysis on key cost and yield drivers will also be presented in the paper. © 2014 IEEE.

Vardaman E.J.,Austin International Inc.
Electronics System Integration Technology Conference, ESTC 2010 - Proceedings | Year: 2010

Performance requirements such as increased bandwidth and lower power are driving the adoption of 3D ICs designed with through silicon vias. Many companies and research organizations have described the advantages of stacking chips vertically. There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. As companies move from R&D into production the difficult work begins in addressing the issues of design, thermal management, test, and assembly. Different needs and economic factors determine the timing of adoption in each application. Issues in moving to volume production include the installation and qualification of high-volume 300mm production lines, assembly and test capability, the availability of TSV interposers, and reliability data. This presentation provides an assessment of the infrastructure for 3D TSV and provides an update on the remaining barriers to adoption.

Palesko C.A.,SavanSys Solutions LLC | Vardaman E.J.,Austin International Inc.
Proceedings - Electronic Components and Technology Conference | Year: 2010

When the cost of gold was $500 per ounce, the lowest cost packaging choice was clear - it was always gold wire bonding. However, with the cost of gold at more than $1,000 per ounce and significant cost decreases in flip chip package fabrication and assembly, the lowest cost packaging choice is no longer obvious. Gold wire bonding is one of the oldest and most mature process, and offers high yields and low processing costs1. Copper wire bonding is an alternative to save material cost, but is less mature and requires equipment modifications2. Historically, flip chip packages have only been cost effective for area-constrained applications given the additional wafer bumping cost and the high substrate cost. However, wafer bumping costs have decreased significantly in the past few years and low-cost flip chip substrates are now available in the market. This poster presentation will compare the total packaging cost from wafer preparation through final package assembly. The analysis will be done using a comprehensive activity based cost model for each of the three package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), substrate fabrication activities (inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) have been modeled and verified using multiple industry sources. © 2010 IEEE.

Lenihan T.G.,Austin International Inc. | Matthew L.,Austin International Inc. | Vardaman E.J.,Austin International Inc.
Proceedings of the 2013 IEEE 15th Electronics Packaging Technology Conference, EPTC 2013 | Year: 2013

Silicon interposers are a technology with a history of multiple incarnations over more than 20 years. Today, interposers with TSVs are considered an alternative to 3D IC structures where die are stacked on top of each other using TSVs. Applications for interposers with TSVs include ASICs for networking applications and FPGAs. Xilinx's Virtex-7 2000T FPGA was one of the first new products using a silicon interposer with TSVs for a partitioned IC design. Co-design with new packaging technology has resulted in a new FPGA that allows reduced system cost and increased performance with lower power. By not having to drive off-chip I/Os across PCB traces to adjacent FPGAs, high-performance applications that have previously used multiple FPGAs can be replaced with a single package solution that provides high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. The key to the performance gains is the partitioning of an FPGA die into four 'slices' that are mounted on a silicon interposer. Is this a unique application or are there other potential applications for interposers in applications with GPUs or ASICs? Today's interposers are passive structures, but there are potential for the use of integrated passives in the interposer. How do these applications differ from the technology introduced in previous generations? This presentation highlights the new drivers for the introduction of silicon interposers. The presentation also examines the latest developments in the infrastructure to support the development of this technology, including suppliers. The article also highlights the differences between adoption of today's interposers and the thin-film on silicon (MCM-D) of the past. © 2013 IEEE.

Held M.,Austin International Inc.
AIChE Annual Meeting, Conference Proceedings | Year: 2013

Prevention and control of ignition sources is the key element in manufacturing and processing of explosives. The fundamental approach of BOS (Basis of Safety) and its application principles will be described. Examples will be given to demonstrate how safe operation principles based on BOS are implemented in inherent plant design for manufacturing of explosives of varying sensitivity and also describe trends in modern plant processes.

Vardaman E.J.,Austin International Inc.
Advancing Microelectronics | Year: 2014

The author, Jan Vardeman, discusses the challenges in the adoption of the three dimensional integrated circuits (3D ICs) with through silicon vias (TSV). Challenges include the bond/debonding process in wafer thinning, thermal dissipation where logic and memory are stacked, and test. Another area that is receiving considerable attention is the micro bump assembly process. The introduction of 3D ICs requires new developments in test methodologies and strategies in design for test. Critical needs must be met in order to improve yields and final assembly and reduce costs. The understanding of interactions between materials and equipment will determine successful implementation of the 3D TSV process.

Vardaman E.J.,Austin International Inc. | Matthew L.,Austin International Inc.
Advancing Microelectronics | Year: 2014

Flip chip has been adopted for a variety of applications for different reasons, and the drivers for its expanded use continue to be performance and form factor. Flip chip interconnect can be found in many device types ranging from high performance logic to multiple devices found in wireless products. Devices such as central processing units (CPUs), graphics processors (GPUs), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGAs), media chips, and other high-performance devices have been using FCIP for over a long period of time. Flip chip continues to be used in automotive electronics, hard disk drives, and watch modules. Some form of bump connection will be used for chip-to-chip, chip-to-wafer, or wafer-to-wafer connections in through silicon via (TSV) technology or interconnection.

Austin International Inc. | Date: 2014-03-19

5th wheel glider hitches.

Austin International Inc. | Date: 2014-05-20

5th wheel glider hitches; tow bars; tie rods, leaf springs, pitman arms, drag links, weight distribution hitches, electric tongue jack, off road lighting, aluminum bumpers, steel bumpers and exhaust stack.

Loading Austin International Inc. collaborators
Loading Austin International Inc. collaborators