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Matsumoto K.,ASET Association of Super Advanced Electronics Technologies | Ibaraki S.,ASET Association of Super Advanced Electronics Technologies | Sueoka K.,ASET Association of Super Advanced Electronics Technologies | Sakuma K.,IBM | And 6 more authors.
Annual IEEE Semiconductor Thermal Measurement and Management Symposium | Year: 2013

The thermal resistance of a three-dimensional (3D) chip stack is evaluated, based on the measured thermal resistances of 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. It is discussed how much heat generation of a 3D chip stack is permitted, when a conventional cooling from the top of a 3D chip stack is assumed. Also, as an additional cooling solution for a 3D chip stack, cooling though a laminate (organic substrate) is considered, and the thermal resistance dependence of a laminate on the thermal via density is experimentally clarified. Based on its measured thermal resistance, it is investigated how much additional heat generation is allowed by cooling through a laminate. © 2013 IEEE. Source


Sueoka K.,ASET Association of Super Advanced Electronics Technologies | Yamada F.,ASET Association of Super Advanced Electronics Technologies | Horibe A.,ASET Association of Super Advanced Electronics Technologies | Kikuchi H.,ASET Association of Super Advanced Electronics Technologies | And 2 more authors.
2011 IEEE 13th Electronics Packaging Technology Conference, EPTC 2011 | Year: 2011

TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose a diagnostic method for TSV defects by using X-ray projection microscopy. By optimizing the image contrast of the X-ray projection micrographs in reference to its X-ray intensity histogram, we could obtain the small defect features in TSVs fast and non-destructively. Comparison between this X-ray observation and the destructive cross sectional observation agreed very well. We also extended the implementation of this X-ray microscope diagnostic method to 8-in. full wafer observation. We investigated the wafers with copper-filled TSVs with 80 μm and 20 μm diameters, and confirmed the feasibility of this method for an in-line process monitoring. © 2011 IEEE. Source


Matsumoto K.,ASET Association of Super Advanced Electronics Technologies | Ibaraki S.,ASET Association of Super Advanced Electronics Technologies | Sato M.,ASET Association of Super Advanced Electronics Technologies | Sakuma K.,ASET Association of Super Advanced Electronics Technologies | And 2 more authors.
Annual IEEE Semiconductor Thermal Measurement and Management Symposium | Year: 2010

Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom of a silicon interposer and cooling from the peripheral of a silicon interposer were proposed and evaluated. Based on the experimentally obtained thermal resistance of lead-free (SnAg) interconnections, the cooling performances of the above two cooling solutions were investigated by modeling and the requirements were clarified. ©2010 IEEE. Source


Matsumoto K.,IBM | Ibaraki S.,ASET Association of Super Advanced Electronics Technologies | Sueoka K.,ASET Association of Super Advanced Electronics Technologies | Sakuma K.,ASET Association of Super Advanced Electronics Technologies | And 8 more authors.
2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 | Year: 2013

In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV (Through-Silicon-Via) have been derived through these measurements. We propose how to estimate the thermal resistances of various 3D chip stacks, by storing these experimental results. Also, how much heat generation of a 3D chip stack is allowed, is discussed. Further, as one of possible new cooling solutions for a 3D chip stack, cooling though a laminate (organic substrate) is considered, and the thermal resistance dependence of a laminate on the thermal via density is experimentally clarified. It is also investigated how the thermal via material and the resin (dielectric) material affect the laminate thermal resistance by simulation. It is then discussed how much additional heat generation is allowed by this cooling though a laminate. © 2013 IEEE. Source


Matsumoto K.,ASET Association of Super Advanced Electronics Technologies | Ibaraki S.,ASET Association of Super Advanced Electronics Technologies | Sueoka K.,ASET Association of Super Advanced Electronics Technologies | Sakuma K.,ASET Association of Super Advanced Electronics Technologies | And 3 more authors.
Annual IEEE Semiconductor Thermal Measurement and Management Symposium | Year: 2011

To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37-41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37-41W/mC) and its adequacy is examined. © 2011 IEEE. Source

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