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Crouch A.L.,SiliconAid Solutions | Potter J.C.,ASSET InterTech Inc.
Proceedings - Design Automation Conference | Year: 2016

In this paper, we describe the use of manufacturing scan-based vectors to structurally assess the frequency of any given semiconductor design, as opposed to the complex and costly effort of creating a functional set of vectors that can actually exercise all of the functions needed to accurately determine if the chip really operates at its rated or advertised frequency. Structural techniques reduce the problem to one of a finite measureable and deterministic set of tests whereas functional vectors can be somewhat subjective unless analyzed, simulated and assessed. The techniques developed and described here were developed on microprocessor designs and were then expanded to cover the general case of an ASIC, SoC, and even FPGA by using static timing analysis, automatic test pattern generation (ATPG) against a path-delay fault model, path selection from STA and using path filtering to eliminate false-paths that would result in an incorrect frequency assessment. © 2016 ACM.


Dworak J.,Southern Methodist University | Crouch A.,ASSET InterTech Inc.
Proceedings of the IEEE VLSI Test Symposium | Year: 2015

Today's chips often contain a wealth of embedded instruments, including sensors, hardware monitors, built-in self-test (BIST) engines, etc. They may process sensitive data that requires encryption or obfuscation and may contain encryption keys and ChipIDs. Unfortunately, unauthorized access to internal registers or instruments through test and debug circuitry can turn design for testability (DFT) logic into a backdoor for data theft, reverse engineering, counterfeiting, and denial-of-service attacks. A compromised chip also poses a security threat to any board or system that includes that chip, and boards have their own security issues. We will provide an overview of some chip and board security concerns as they relate to DFT hardware and will briefly review several ways in which the new IEEE 1687 standard can be made more secure. We will then discuss the need for an IEEE Security Standard that can provide solutions and metrics for providing appropriate security matched to the needs of a real world environment. © 2015 IEEE.


Crouch A.,ASSET InterTech Inc. | Dworak J.,Southern Methodist University
Electronic Device Failure Analysis | Year: 2011

Al Crouch and Jennifer Dworak focus on the 3-D Test, explaining how IEEE Standards Help.3-D silicon integration is different from 3-D packaging in that 3-D packaging involves whole packaged chips, and each chip can still be tested individually throughout the manufacturing and assembly process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. What are the test and debug problems with 3-D silicon integration that are different from both 2-D silicon or 3-D packaging? Obviously, the base die is very much like a conventional 2-D die or a 2-D die used for 3-D packaging in that it has pins and probe pads, and these connections can be brought out to both the top and bottom of a package. The base die for 3-D integration has the addition of bumped connections on top of the planarized bare die to allow the direct connection of an upper die.


Ley A.,ASSET InterTech Inc.
SMT Surface Mount Technology Magazine | Year: 2013

Although intrusive test technologies on the manufacturing floor such as ICT have been effective in the past, recent advancements in basic electronic technologies are disrupting legacy test methods. Now, non-intrusive board testing is replacing the intrusive types, such as in-circuit testing.


Waller R.,ASSET InterTech Inc.
Electronics World | Year: 2013

The defects caused by process variances come in a variety of shapes and sizes. Traces on boards may look fine one day and have one or more of these defects the next. Any one of these defects may or may not have an impact on serdes performance, since most designs are developed with a certain level of confidence in their operating margins, but the cumulative effects of several defects may downgrade the performance of a serdes. In addition, identifying a process that is heading towards out of specification could give the manufacturer a chance to correct the problem before it becomes disastrous. One of the big advantages of some implementations of embedded instrumentation is it can monitor serdes performance at the receiver and report test results to a software-driven external test platform. Cumbersome and less-than-effective external fixtures are avoided. In some cases, the instrumentation embedded in a board?s chips can also detect structural and functional faults.


Patent
ASSET InterTech Inc. | Date: 2014-10-07

A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment.


Trademark
ASSET InterTech Inc. | Date: 2010-11-09

Computer programs providing scan management for use in the testing of circuits and circuit boards to verify that the circuits function properly.


Trademark
ASSET InterTech Inc. | Date: 2014-03-11

Downloadable computer software programs for use in the testing of circuits and circuit boards to verify that the circuits function properly.


A system and method of debugging application software operating on a system-on-chip processor (SOC) with a system trace macrocell.


Trademark
ASSET InterTech Inc. | Date: 2016-03-02

Computer programs, namely, computer programs for debugging, tracing, analyzing and testing of embedded software and firmware of processors to find coding problems and verify that the software and the firmware function properly.

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