Kista, Sweden
Kista, Sweden

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Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: NMBP-02-2016 | Award Amount: 8.05M | Year: 2017

Silicon carbide presents a high breakdown field (2-4 MV/cm) and a high energy band gap (2.33.2 eV), largely higher than for silicon. Within this frame, the cubic polytype of SiC (3C-SiC) is the only one that can be grown on a host substrate with the huge opportunity to grow only the silicon carbide thickness required for the targeted application. The possible growth on silicon substrate has remained for long period a real advantage in terms of scalability regarding the reduced diameter of hexagonal SiC wafer commercially available. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. The lowering of the conduction band minimum brings about a reduced density of states at the SiO2/3C-SiC interface and MOSFET on 3C-SiC has demonstrated the highest channel mobility of above 300 cm2/(Vxs) ever achieved on SiC crystals, prompting a remarkable reduction in the power consumption of these power switching devices. The electrical activity of extended defects in 3C SiC is a major concern for electronic device functioning. To achieve viable commercial yields the mechanisms of defects must be understood and methods for their reduction developed.. In this project new approaches for the reduction of defects will be used, working on new compliance substrates that can help to reduce the stress and the defect density at the same time. This growth process will be driven by numerical simulations of the growth and simulations of the stress reduction. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized inside the project.


Grant
Agency: European Commission | Branch: FP7 | Program: CP-IP | Phase: NMP.2013.2.2-3 | Award Amount: 18.59M | Year: 2014

Highly efficient Power Electronics (PE) employed in power generation, transmission, and distribution is the prerequisite for the Europe-wide penetration of renewable energies; improves the energy efficiency; increases the power quality and enables continuous voltage regulation, reactive power compensation and automated distribution. It also facilitates the integration of distributed resources like local energy storages, photovoltaic generators, and plug-in electric vehicles. The development of a new generation of high power semiconductor devices, able to operate above 10kV, is crucial for reducing the cost of PE in the above-mentioned applications. The material properties of SiC, clearly superior to those of Si, will lead to enhanced power devices with much better performance than conventional Si devices. However, todays SiC PE performs rather poorly compared to the predictions and the production costs are by far too high. Pooling world-leading manufacturers and researchers, SPEED aims at a breakthrough in SiC technology along the whole supply chain: Growth of SiC substrates and epitaxial-layers. Fabrication of power devices in the 1.7/>10kV range. Packaging and reliability testing. SiC-based highly efficient power conversion cells. Real-life applications and field-tests in close cooperation with two market-leading manufacturers of high-voltage (HV) devices. Known and new methodologies will be adapted to SiC devices and optimized to make them a practical reality. The main targets are cost-savings and superior power quality using more efficient power converters that exploit the reduced power losses of SiC. To this end, suitable SiC substrates, epitaxial-layers, and HV devices shall be developed and eventually be implemented in two demonstrators: A cost-efficient solid-state transformer to support advanced grid smartness and power quality. A windmill power converter with improved capabilities for generating AC and DC power.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-01-2014 | Award Amount: 4.49M | Year: 2015

OSIRIS project, a Research and Innovation Action (RIA), aims at improving substantially the cost effectiveness and performance of gallium nitride (GaN) based millimetre wave components. The project proposes to elaborate innovative SiC material using isotopic sources. This material will offer thermal conductivity improvement of 30% which is important for devices dissipating a lot of power, in particular in SiC power electronics and in microwave device using GaN high electron mobility transistors (HEMT) grown on SiC semi-insulating substrates. OSIRIS project will allow reinforcing GaN technology penetration into the market by cost effectiveness of the SiC substrates and circuit performances improvement thanks to better heat spreading close to the dissipative area. For microwave GaN/SiC HEMT this isotopic approach could create a complete shift in the currently used substrate / GaN epi-wafer technology; it intends to grow high thermal conductivity (\30%) semi-insulating SiC on top of low cost semiconducting SiC substrates (widely used by the power electronics and LED industries). Reduced layer thickness is necessary as only the top 50 to 100m SiC wafer is really useful as the substrate itself is currently thinned to realise microstrip waveguided microwave circuits. For power electronics, this isotopic innovation will be essentially focused on thermal improvement, i.e. better electron mobility at a given power dissipation as mobility and drift mobility decrease with temperature and also better carrier transport thanks to lower scattering rates. Schottky and p-i-n diodes will be tested using this material, which however will have to be doped while microwave devices need semi-insulating materials. The improved thermal SiC properties will be obtained by using single isotopic atoms for silicon and carbon, namely 28Si and 12C. The SiC wafer size will be targeted to 100mm (4-inches) which is today widely used on industry.


Mikhaylov A.I.,Acreo Ab | Afanasyev A.V.,SPbETU LETI | Luchinin V.V.,SPbETU LETI | Reshanov S.A.,Ascatron AB | And 2 more authors.
Materials Research Society Symposium Proceedings | Year: 2014

An alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs). Copyright © 2014 Materials Research Society.


Reshanov S.A.,Ascatron AB | Schoner A.,Ascatron AB | Kaplan W.,Acreo Ab | Zhang A.,Ascatron AB | And 2 more authors.
ECS Transactions | Year: 2014

The paper presents the advanced concept of fully epitaxial SiC junction barrier Schottky (JBS) diodes. It combines trench etching with embedded epitaxial re-growth and enables cost-efficient manufacturing. Fabricated devices are rated for 20A / 1200V and have leakage currents below 0.1μA at 1000V blocking voltage. © The Electrochemical Society.


Schoner A.,Ascatron AB | Elahipanah H.,Ascatron AB | Thierry-Jebali N.,Ascatron AB | Reshanov S.A.,Ascatron AB | And 4 more authors.
ECS Transactions | Year: 2016

Buried grid technology is suggested to protect field sensitive device areas from high electric field in order to improve the high temperature and high voltage performance of SiC devices. More than three orders of magnitude lower leakage currents have been demonstrated at high temperature operation. The drawback is that the total resistance increases due to the introduction of the buried grid leading to higher voltage drop at rated current and higher conduction losses. In this paper, we discuss doping and barrier engineering methods in order to take full advantage of the superior shielding effect of the buried grid technology and at the same time minimize the effect on the current conduction. As example, the design considerations for a 1200 V SiC buried grid JBS diode in terms of epi structure doping as well as buried grid properties is comprehensively investigated to optimize the on-state condition. © The Electrochemical Society.


Ilyin V.A.,Saint Petersburg Electrotechnical University | Afanasyev A.V.,Saint Petersburg Electrotechnical University | Ivanov B.V.,Saint Petersburg Electrotechnical University | Kardo-Sysoev A.F.,RAS Ioffe Physical - Technical Institute | And 5 more authors.
Materials Science Forum | Year: 2016

The paper reports on the results of the studies of static and dynamic characteristics of 4HSiC drift step recovery diodes (DSRDs) assembled in diode stacks. Switching performance of single dies has been simulated and experimentally confirmed. It was established that the switching process is determined primarily by the incomplete ionization of acceptors in 4H-SiC and by the bandgap narrowing in heavily doped emitters. Based on the simulation results the optimized die size has been selected. For DSRD stacks of 4 and 8 dies I-V and C-V measurements are reported. The stacks were dynamically tested in a special oscillator circuit. Repetitive voltage pulses of 10.5 kV with the leading edge length of 900 ps were demonstrated. © 2016 Trans Tech Publications, Switzerland.


Mikhaylov A.I.,Ascatron AB | Reshanov S.A.,Ascatron AB | Schoner A.,Ascatron AB | Afanasyev A.V.,SPbETULETI' | And 5 more authors.
Materials Science Forum | Year: 2016

High channel mobility 4H-SiC MOSFETs have been demonstrated by phosphorus and arsenic implantation prior to thermal oxidation in N2O. The maximum field-effect mobility of 81 and 114 cm2/Vs were achieved, respectively. The MOSFET fabrication was done on lightly aluminium doped p-type epitaxial layers and on heavily aluminium implanted p-well. © 2016 Trans Tech Publications, Switzerland.


Gysin U.,University of Basel | Glatzel T.,University of Basel | Schmolzer T.,ABB | Schoner A.,Ascatron AB | And 3 more authors.
Beilstein Journal of Nanotechnology | Year: 2015

Background: The resolution in electrostatic force microscopy (EFM), a descendant of atomic force microscopy (AFM), has reached nanometre dimensions, necessary to investigate integrated circuits in modern electronic devices. However, the characterization of conducting or semiconducting power devices with EFM methods requires an accurate and reliable technique from the nanometre up to the micrometre scale. For high force sensitivity it is indispensable to operate the microscope under high to ultrahigh vacuum (UHV) conditions to suppress viscous damping of the sensor. Furthermore, UHV environment allows for the analysis of clean surfaces under controlled environmental conditions. Because of these requirements we built a large area scanning probe microscope operating under UHV conditions at room temperature allowing to perform various electrical measurements, such as Kelvin probe force microscopy, scanning capacitance force microscopy, scanning spreading resistance microscopy, and also electrostatic force microscopy at higher harmonics. The instrument incorporates beside a standard beam deflection detection system a closed loop scanner with a scan range of 100 μm in lateral and 25 μm in vertical direction as well as an additional fibre optics. This enables the illumination of the tip-sample interface for optically excited measurements such as local surface photo voltage detection. Results: We present Kelvin probe force microscopy (KPFM) measurements before and after sputtering of a copper alloy with chromium grains used as electrical contact surface in ultra-high power switches. In addition, we discuss KPFM measurements on cross sections of cleaved silicon carbide structures: a calibration layer sample and a power rectifier. To demonstrate the benefit of surface photo voltage measurements, we analysed the contact potential difference of a silicon carbide p/n-junction under illumination. © 2015 Gysin et al; licensee Beilstein-Institut.


PubMed | University of Basel, ABB and Ascatron AB
Type: | Journal: Beilstein journal of nanotechnology | Year: 2016

The resolution in electrostatic force microscopy (EFM), a descendant of atomic force microscopy (AFM), has reached nanometre dimensions, necessary to investigate integrated circuits in modern electronic devices. However, the characterization of conducting or semiconducting power devices with EFM methods requires an accurate and reliable technique from the nanometre up to the micrometre scale. For high force sensitivity it is indispensable to operate the microscope under high to ultra-high vacuum (UHV) conditions to suppress viscous damping of the sensor. Furthermore, UHV environment allows for the analysis of clean surfaces under controlled environmental conditions. Because of these requirements we built a large area scanning probe microscope operating under UHV conditions at room temperature allowing to perform various electrical measurements, such as Kelvin probe force microscopy, scanning capacitance force microscopy, scanning spreading resistance microscopy, and also electrostatic force microscopy at higher harmonics. The instrument incorporates beside a standard beam deflection detection system a closed loop scanner with a scan range of 100 m in lateral and 25 m in vertical direction as well as an additional fibre optics. This enables the illumination of the tip-sample interface for optically excited measurements such as local surface photo voltage detection.We present Kelvin probe force microscopy (KPFM) measurements before and after sputtering of a copper alloy with chromium grains used as electrical contact surface in ultra-high power switches. In addition, we discuss KPFM measurements on cross sections of cleaved silicon carbide structures: a calibration layer sample and a power rectifier. To demonstrate the benefit of surface photo voltage measurements, we analysed the contact potential difference of a silicon carbide p/n-junction under illumination.

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