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Cambridge, United Kingdom

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Patent
ARM Ltd | Date: 2017-02-01

Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more elements , according to the state of respective predicate flags, for controlling looped vector operations ; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute decoded instructions; wherein the instruction decoder circuitry is responsive to a CHANGE instruction which, when executed, modifies a variable (such as a loop control variable) by an amount dependent upon a number of active predicate flags, and can therefore set the amount of the change according to the vector length of the system by which the instruction is being executed. This can allow the same program instructions to be executed, without necessarily requiring recompilation, on different instances of the vector processing circuitry having different respective available vector lengths.


A method for generating a profile of a target program executed by a target data processing apparatus comprises performing at least one profile updating operation. Each profile updating operation includes identifying based on at least one waypoint marker indicating an outcome of a corresponding waypoint instruction of a target program, a next block of instructions executed by the target data processing apparatus during execution of the target program; determining whether a target entry for the next block of instructions is present in a profile cache; when the target entry is present updating the profile of the target program according to zero, one or more profile updating actions specified by the target entry. When the target entry is absent, any profile updating actions can be determined based on an instruction-by-instruction representation of the target program. This approach helps to speed up instruction-based summaries from program flow trace.


Grant
Agency: European Commission | Branch: H2020 | Program: IA | Phase: ICT-26-2014 | Award Amount: 10.78M | Year: 2015

Following the trends of the creation of the The Internet of Things (IoT) and the rapid penetration of SSL based lighting, it is very advantageous to connect the luminaires in buildings to the Internet. OpenAIS aims at setting the leading standard for inclusion of lighting for professional applications in to IoT, with a focus on office lighting. This will enable a transition from the currently existing closed and command oriented lighting control systems to an open and service oriented system architecture. Openness and service orientation will create an eco-system of suppliers of interoperable components and a market for apps that exploit the lighting system to add value beyond the lighting function. Added value can e.g. be related to more efficient use of the building, reduction of carbon footprint and increased comfort and wellbeing. In addition, IoT will facilitate smooth and effective interaction of the lighting system with other functions in a building such as e.g. HVAC, security and access control. Extensibility and security of the system architecture are important aspects and will be guaranteed. The OpenAIS project will define the requirements and use cases for offices in 2020, define the best open system architecture, identify existing ICT components to be used and develop additional components. The system will be validated by a pilot installation in a real office setting. After the OpenAIS project, the Consortium will pursue standardization of the system architecture, aiming at the creation of the leading standard for Internet connected lighting. The project brings together a strong collaboration of the leading lighting companies Zumtobel, Tridonic, and Philips and the major players in IoT technology ARM, NXP and Imtech. Consortium partner Johnson Controls represents the end user and academic knowledge on ICT and system architecture is present through TU/e and TNO-ESI. During the project, the Consortium will seek close cooperation with the IoT community.


Grant
Agency: GTR | Branch: EPSRC | Program: | Phase: Research Grant | Award Amount: 567.20K | Year: 2016

Energy efficiency is one of the primary design constraints for modern processing systems. Hardware accelerators are seen as a key technology to address the high performance with limited energy issue. In addition the arrival of computing languages such as OpenCL offer a route to the programmer to target different types of multi-core accelerators using a single source code. Performance portability is a significant challenge specially if the accelerators have different microarchitectures such as is the case in CPU-GPU-FPGA systems. This research addresses the energy and performance challenge by investigating how a device formed by processing units with different granularities ranging from coarse grain CPU cores of different complexity, medium grain general purpose GPU cores and fine grain FPGA logic cells can be dynamically programmed. The challenge is to be able to program all these resources with a single programming model and create a run-time system that can automatically tune the software to the best execution resource from energy and performance points of view. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 8.63M | Year: 2015

ExaNoDe will investigate, develop and pilot (technology readiness level 7) a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing and demonstrated using hardware-emulated interconnect. It will build on multiple European initiatives for scalable computing, utilizing low-power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels. The ExaNoDe compute element aims towards exascale compute goals through: Integration of the most advanced low-power processors and accelerators across scalar, SIMD, GPGPU and FPGA processing elements supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; The development of an instantiation of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and the evaluation, tuning and analysis of HPC mini-apps. Each aspect of ExaNoDE is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications, their requirements and the tuning of their kernels.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 7.97M | Year: 2015

The main target of the Mont-Blanc 3 project European Scalable and power efficient HPC platform based on low-power embedded technology is the creation of a new high-end HPC platform (SoC and node) that is able to deliver a new level of performance / energy ratio whilst executing real applications. The technical objectives are: 1. To design a well-balanced architecture and to deliver the design for an ARM based SoC or SoP (System on Package) capable of providing pre-exascale performance when implemented in the time frame of 2019-2020. The predicted performance target must be measured using real HPC applications. 2. To maximise the benefit for HPC applications with new high-performance ARM processors and throughput-oriented compute accelerators designed to work together within the well-balanced architecture. 3. To develop the necessary software ecosystem for the future SoC. This additional objective is important to maximize the impact of the project and make sure that this ARM architecture path will be successful in the market. The project shall build upon the previous Mont-Blanc & Mont-Blanc 2 FP7 projects, with ARM, BSC & Bull being involved in Mont-Blanc 1, 2 and 3 projects. It will adopt a co-design approach to make sure that the hardware and system innovations are readily translated into benefits for HPC applications. This approach shall integrate architecture work (WP3 & 4 - on balanced architecture and computing efficiency) together with a simulation work (to feed and validate the architecture studies ) and work on the needed software ecosystem.


Grant
Agency: European Commission | Branch: H2020 | Program: CSA | Phase: ICT-04-2015 | Award Amount: 3.48M | Year: 2016

HiPEAC is a support action that aims to structure and strengthen the European academic and industrial communities in computing systems: (i) by increasing innovation awareness and by encouraging researchers to engage in innovation activities; (ii) by professionally disseminating program achievements beyond the traditional scientific venues; (iii) by producing a vision document including recommendations on how to improve the innovation potential of H2020 projects, and (iv) by growing the computing systems community beyond 2000 active members in Europe. The HiPEAC support action is meant to be the continuation of three successful FP7 networks of excellence with the same name (HiPEAC1-3). This support action will leverage the existing community, the expertise and the set of instruments that were developed since 2004 and work on the objectives of this support action: cross-sectorial platform-building, clustering of related research projects, structuring the European academic and industrial research communities, dissemination of programme achievements, impact analysis, constituency building and roadmapping for future research and innovation agendas. The overall approach of the HiPEAC support action is that it wants to bring together all actors and stakeholders in the computing systems community in Europe - especially EU-funded projects and SMEs - in one well managed structure where they can interact, disseminate/share information, transfer knowledge/technology, exchange human resources, think about their future challenges, experiment with ideas to strengthen the community, etc. The HiPEAC support action will support its members and projects with tasks that are too difficult/complex to carry out individually: vision building, professional communication, recruitment, event management at the European level. By offering such services a burden is taken away from the projects and members. They can then focus on the content, and the impact of their efforts is amplified.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 8.00M | Year: 2016

Modular Microserver DataCentre (M2DC) will investigate, develop and demonstrate (Technology Readiness Level 7) a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources, being able to be tailored to meet requirements from various application domains such as image processing, cloud computing or even HPC. To achieve this objective, M2DC will be built on three main pillars: - [Pillar 1] A flexible server architecture that can be easily customised, maintained and updated so as to enable adaptation of the data centre. Open server architecture will enable integration of computing resources with constrained thermal power dissipation such as embedded CPUs, GPUs, FPGAs, manycore processors integrated using established standards such as COM Express. - [Pillar 2] Advanced management strategies [Pillar 2a] and system efficiency enhancements (SEE) [Pillar 2b] will improve the behaviour of the system during runtime. The server architecture will include built-in enhancements (e.g., for computing acceleration, energy efficiency, dependability and security, behaviour monitoring, etc.) on system level. - [Pillar 3] Well-defined interfaces to surrounding software ecosystem will allow for an easy integration into existing data centre management solutions through the use of the latest middleware software for resource management, provisioning, etc. The results of these three pillars will be combined to produce TCO (Total Cost of Ownership)-optimized appliances, deployed in a real data centre environment and seamlessly interacting with existing infrastructure to run real-life applications.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 4.82M | Year: 2016

The projects principal aim is the development of UniServer: a universal system architecture and software ecosystem for servers. UniServer will facilitate the evolution of the Internet from an infrastructure where data is aggregated to centralized data-centres to an infrastructure where data are handled in a distributed and localized manner close to the data sources. UniServer will realize its bold goal by greatly improving the energy efficiency, performance, dependability and security of the current state-of-the-art micro-servers, while reinforcing the supported system software. UniServer will develop effective means to expose the intrinsic hardware heterogeneity caused by process variations, harness it and use it to its advantage for improving energy efficiency or performance. Lightweight, only software, mechanisms will be embedded for exposing to the system software the pessimistic voltage/frequency margins currently adopted in commercial processor and memory, which will be enhanced with new margin/fault-aware runtime and resource management policies. The UniServer technology will be ported on the world-first 64-bit ARM based Server-on-Chip and evaluated using smart emerging applications deployed in classical cloud business data-centres as well as in new environments closer to the data sources. UniServer aspires to deliver a unique fully working prototype that will turn the opportunities in the emerging Big Data and IoT markets into real, smarter products that can improve the everyday life and lead to a substantial financial and employment growth. The unique blend of expertise of UniServers consortium consisting of world leading low-power processor and Server-on-Chip suppliers (ARM, APM) as well as system software developer (IBM), and a set of emerging application drivers and established research organisations guarantees the successful realization of the ambitious goals, while reinforcing Europes strong position in traditional and new multi-billion euro market.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-01-2016 | Award Amount: 8.59M | Year: 2016

The Bonseyes project aims to develop a platform consisting of a Data Marketplace, Deep Learning Toolbox, and Developer Reference Platforms for organizations wanting to adopt Artificial Intelligence in low power IoT devices (edge computing), embedded computing systems, or data center servers (cloud computing). It will bring about orders of magnitude improvements in efficiency, performance, reliability, security, and productivity in the design and programming of Systems of Artificial Intelligence that incorporate Smart Cyber Physical Systems while solving a chicken-egg problem for organizations who lack access to Data and Models. Its open software architecture will facilitate adoption of the whole concept on a wider scale. It aims to address one of the most significant trends in the Internet of Things which is the shifting balance between edge computing and cloud computing. The early days of the IoT have been characterized by the critical role of cloud platforms as application enablers. Intelligent systems have largely relied on the cloud level for their intelligence, and the actual devices of which they consist have been relatively unsophisticated. This old premise is currently being shaken up, as the computing capabilities on the edge level advance faster than those of the cloud level. This paradigm shiftfrom the connected device paradigm to the intelligent device paradigm opens up numerous opportunities. To evaluate the effectiveness, technical feasibility, and to quantify the real-world improvements in efficiency, security, performance, effort and cost of adding AI to products and services using the Bonseyes platform, four complementary demonstrators will be built: Automotive Intelligent Safety, Automotive Cognitive Computing, Consumer Emotional Virtual Agent, and Healthcare Patient Monitoring. Bonseyes platform capabilities are aimed at being aligned with the European FI-PPP activities and take advantage of its flagship project FIWARE.

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