Cambridge, United Kingdom
Cambridge, United Kingdom

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Systems and methods for application level authentication are provided for use with the low energy Bluetooth device and accessory. This includes receiving accessory credentials from a server, establishing a Bluetooth low energy connection with the accessory, authenticating with the accessory, and lastly transferring data to the accessory. The transferring of the data may be either a bulk transfer, or a data stream. The authenticating may be an application layer authentication between a device and the accessory using a shared secret key and using a hash function. Additional embodiments include methods for over-the-air firmware updates, and device control of a low energy Bluetooth accessory.


Patent
ARM Ltd | Date: 2017-01-09

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.


Patent
ARM Ltd | Date: 2017-05-17

A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.


Patent
ARM Ltd | Date: 2017-02-03

Apparatus is provided comprising an electrical motor comprising a rotor and a stator, the rotor comprising a plurality of rotor teeth and the stator comprising a plurality of stator teeth. The apparatus has a driver circuit to drive the electrical motor comprising a boost converter comprising a charge storage element and coupled to a first terminal of a coil winding on at least one of the plurality of stator teeth, and a buck converter comprising the same charge storage element and coupled to the same first terminal of the coil winding on the at least one of the plurality of stator teeth. An inductive element of the boost converter and the buck converter is provided by the coil winding of the at least one of the plurality of stator teeth, and the charge storage element is referenced to a supply node for coupling the second terminal of the coil winding to an electrical supply.


A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative. Conversely if the modification to the call stack is to be made at a relative stacking position which is not in a positive growth direction with respect to the position indicated by the copy stored, then that modification is labelled as speculative. The size of the write-set associated with maintaining the call stack whilst in transactional execution mode can therefore be reduced.


Patent
ARM Ltd | Date: 2017-02-14

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.


Grant
Agency: European Commission | Branch: H2020 | Program: CSA | Phase: ICT-04-2015 | Award Amount: 3.48M | Year: 2016

HiPEAC is a support action that aims to structure and strengthen the European academic and industrial communities in computing systems: (i) by increasing innovation awareness and by encouraging researchers to engage in innovation activities; (ii) by professionally disseminating program achievements beyond the traditional scientific venues; (iii) by producing a vision document including recommendations on how to improve the innovation potential of H2020 projects, and (iv) by growing the computing systems community beyond 2000 active members in Europe. The HiPEAC support action is meant to be the continuation of three successful FP7 networks of excellence with the same name (HiPEAC1-3). This support action will leverage the existing community, the expertise and the set of instruments that were developed since 2004 and work on the objectives of this support action: cross-sectorial platform-building, clustering of related research projects, structuring the European academic and industrial research communities, dissemination of programme achievements, impact analysis, constituency building and roadmapping for future research and innovation agendas. The overall approach of the HiPEAC support action is that it wants to bring together all actors and stakeholders in the computing systems community in Europe - especially EU-funded projects and SMEs - in one well managed structure where they can interact, disseminate/share information, transfer knowledge/technology, exchange human resources, think about their future challenges, experiment with ideas to strengthen the community, etc. The HiPEAC support action will support its members and projects with tasks that are too difficult/complex to carry out individually: vision building, professional communication, recruitment, event management at the European level. By offering such services a burden is taken away from the projects and members. They can then focus on the content, and the impact of their efforts is amplified.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 8.00M | Year: 2016

Modular Microserver DataCentre (M2DC) will investigate, develop and demonstrate (Technology Readiness Level 7) a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources, being able to be tailored to meet requirements from various application domains such as image processing, cloud computing or even HPC. To achieve this objective, M2DC will be built on three main pillars: - [Pillar 1] A flexible server architecture that can be easily customised, maintained and updated so as to enable adaptation of the data centre. Open server architecture will enable integration of computing resources with constrained thermal power dissipation such as embedded CPUs, GPUs, FPGAs, manycore processors integrated using established standards such as COM Express. - [Pillar 2] Advanced management strategies [Pillar 2a] and system efficiency enhancements (SEE) [Pillar 2b] will improve the behaviour of the system during runtime. The server architecture will include built-in enhancements (e.g., for computing acceleration, energy efficiency, dependability and security, behaviour monitoring, etc.) on system level. - [Pillar 3] Well-defined interfaces to surrounding software ecosystem will allow for an easy integration into existing data centre management solutions through the use of the latest middleware software for resource management, provisioning, etc. The results of these three pillars will be combined to produce TCO (Total Cost of Ownership)-optimized appliances, deployed in a real data centre environment and seamlessly interacting with existing infrastructure to run real-life applications.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 4.82M | Year: 2016

The projects principal aim is the development of UniServer: a universal system architecture and software ecosystem for servers. UniServer will facilitate the evolution of the Internet from an infrastructure where data is aggregated to centralized data-centres to an infrastructure where data are handled in a distributed and localized manner close to the data sources. UniServer will realize its bold goal by greatly improving the energy efficiency, performance, dependability and security of the current state-of-the-art micro-servers, while reinforcing the supported system software. UniServer will develop effective means to expose the intrinsic hardware heterogeneity caused by process variations, harness it and use it to its advantage for improving energy efficiency or performance. Lightweight, only software, mechanisms will be embedded for exposing to the system software the pessimistic voltage/frequency margins currently adopted in commercial processor and memory, which will be enhanced with new margin/fault-aware runtime and resource management policies. The UniServer technology will be ported on the world-first 64-bit ARM based Server-on-Chip and evaluated using smart emerging applications deployed in classical cloud business data-centres as well as in new environments closer to the data sources. UniServer aspires to deliver a unique fully working prototype that will turn the opportunities in the emerging Big Data and IoT markets into real, smarter products that can improve the everyday life and lead to a substantial financial and employment growth. The unique blend of expertise of UniServers consortium consisting of world leading low-power processor and Server-on-Chip suppliers (ARM, APM) as well as system software developer (IBM), and a set of emerging application drivers and established research organisations guarantees the successful realization of the ambitious goals, while reinforcing Europes strong position in traditional and new multi-billion euro market.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-01-2016 | Award Amount: 8.59M | Year: 2016

The Bonseyes project aims to develop a platform consisting of a Data Marketplace, Deep Learning Toolbox, and Developer Reference Platforms for organizations wanting to adopt Artificial Intelligence in low power IoT devices (edge computing), embedded computing systems, or data center servers (cloud computing). It will bring about orders of magnitude improvements in efficiency, performance, reliability, security, and productivity in the design and programming of Systems of Artificial Intelligence that incorporate Smart Cyber Physical Systems while solving a chicken-egg problem for organizations who lack access to Data and Models. Its open software architecture will facilitate adoption of the whole concept on a wider scale. It aims to address one of the most significant trends in the Internet of Things which is the shifting balance between edge computing and cloud computing. The early days of the IoT have been characterized by the critical role of cloud platforms as application enablers. Intelligent systems have largely relied on the cloud level for their intelligence, and the actual devices of which they consist have been relatively unsophisticated. This old premise is currently being shaken up, as the computing capabilities on the edge level advance faster than those of the cloud level. This paradigm shiftfrom the connected device paradigm to the intelligent device paradigm opens up numerous opportunities. To evaluate the effectiveness, technical feasibility, and to quantify the real-world improvements in efficiency, security, performance, effort and cost of adding AI to products and services using the Bonseyes platform, four complementary demonstrators will be built: Automotive Intelligent Safety, Automotive Cognitive Computing, Consumer Emotional Virtual Agent, and Healthcare Patient Monitoring. Bonseyes platform capabilities are aimed at being aligned with the European FI-PPP activities and take advantage of its flagship project FIWARE.

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