ARM Ltd.

Cambridge, United Kingdom
Cambridge, United Kingdom
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Patent
ARM Ltd | Date: 2016-10-26

An apparatus comprises instruction fetch circuitry to retrieve instructions from storage and branch target storage to store entries comprising source and target addresses for branch instructions. A confidence value is stored with each entry and when a current address matches a source address in an entry, and the confidence value exceeds a confidence threshold, instruction fetch circuitry retrieves a predicted next instruction from a target address in the entry. Branch confidence update circuitry increases the confidence value of the entry on receipt of a confirmation of the target address and decreases the confidence value on receipt of a non-confirmation of the target address. When the confidence value meets a confidence lock threshold below the confidence threshold and non-confirmation of the target address is received, a locking mechanism with respect to the entry is triggered. A corresponding method is also provided.


Patent
ARM Ltd | Date: 2016-11-09

A display controller 10 comprises a first display processing core 20 comprising a first input stage operable to read at least one input surface, a first processing stage operable to generate an output surface, a first output stage operable to provide an output surface for display to a first display 3, and a first write-out stage 27 operable to write data of an output surface to external memory 1, and a second display processing core 40 comprising a second input stage operable to read at least one input surface, a second processing stage operable to generate an output surface, and a second output stage operable to provide an output surface for display to a second display 5. The display controller 10 also comprises an internal data path 30 for passing data of an output surface from the first display core 20 to the second display core 40.


Patent
ARM Ltd | Date: 2016-11-14

A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.


Patent
ARM Ltd | Date: 2017-05-17

A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.


Grant
Agency: European Commission | Branch: H2020 | Program: IA | Phase: ICT-26-2014 | Award Amount: 10.78M | Year: 2015

Following the trends of the creation of the The Internet of Things (IoT) and the rapid penetration of SSL based lighting, it is very advantageous to connect the luminaires in buildings to the Internet. OpenAIS aims at setting the leading standard for inclusion of lighting for professional applications in to IoT, with a focus on office lighting. This will enable a transition from the currently existing closed and command oriented lighting control systems to an open and service oriented system architecture. Openness and service orientation will create an eco-system of suppliers of interoperable components and a market for apps that exploit the lighting system to add value beyond the lighting function. Added value can e.g. be related to more efficient use of the building, reduction of carbon footprint and increased comfort and wellbeing. In addition, IoT will facilitate smooth and effective interaction of the lighting system with other functions in a building such as e.g. HVAC, security and access control. Extensibility and security of the system architecture are important aspects and will be guaranteed. The OpenAIS project will define the requirements and use cases for offices in 2020, define the best open system architecture, identify existing ICT components to be used and develop additional components. The system will be validated by a pilot installation in a real office setting. After the OpenAIS project, the Consortium will pursue standardization of the system architecture, aiming at the creation of the leading standard for Internet connected lighting. The project brings together a strong collaboration of the leading lighting companies Zumtobel, Tridonic, and Philips and the major players in IoT technology ARM, NXP and Imtech. Consortium partner Johnson Controls represents the end user and academic knowledge on ICT and system architecture is present through TU/e and TNO-ESI. During the project, the Consortium will seek close cooperation with the IoT community.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: FETHPC-1-2014 | Award Amount: 8.63M | Year: 2015

ExaNoDe will investigate, develop and pilot (technology readiness level 7) a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing and demonstrated using hardware-emulated interconnect. It will build on multiple European initiatives for scalable computing, utilizing low-power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels. The ExaNoDe compute element aims towards exascale compute goals through: Integration of the most advanced low-power processors and accelerators across scalar, SIMD, GPGPU and FPGA processing elements supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; The development of an instantiation of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and the evaluation, tuning and analysis of HPC mini-apps. Each aspect of ExaNoDE is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications, their requirements and the tuning of their kernels.


Grant
Agency: European Commission | Branch: H2020 | Program: CSA | Phase: ICT-04-2015 | Award Amount: 3.48M | Year: 2016

HiPEAC is a support action that aims to structure and strengthen the European academic and industrial communities in computing systems: (i) by increasing innovation awareness and by encouraging researchers to engage in innovation activities; (ii) by professionally disseminating program achievements beyond the traditional scientific venues; (iii) by producing a vision document including recommendations on how to improve the innovation potential of H2020 projects, and (iv) by growing the computing systems community beyond 2000 active members in Europe. The HiPEAC support action is meant to be the continuation of three successful FP7 networks of excellence with the same name (HiPEAC1-3). This support action will leverage the existing community, the expertise and the set of instruments that were developed since 2004 and work on the objectives of this support action: cross-sectorial platform-building, clustering of related research projects, structuring the European academic and industrial research communities, dissemination of programme achievements, impact analysis, constituency building and roadmapping for future research and innovation agendas. The overall approach of the HiPEAC support action is that it wants to bring together all actors and stakeholders in the computing systems community in Europe - especially EU-funded projects and SMEs - in one well managed structure where they can interact, disseminate/share information, transfer knowledge/technology, exchange human resources, think about their future challenges, experiment with ideas to strengthen the community, etc. The HiPEAC support action will support its members and projects with tasks that are too difficult/complex to carry out individually: vision building, professional communication, recruitment, event management at the European level. By offering such services a burden is taken away from the projects and members. They can then focus on the content, and the impact of their efforts is amplified.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 8.00M | Year: 2016

Modular Microserver DataCentre (M2DC) will investigate, develop and demonstrate (Technology Readiness Level 7) a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources, being able to be tailored to meet requirements from various application domains such as image processing, cloud computing or even HPC. To achieve this objective, M2DC will be built on three main pillars: - [Pillar 1] A flexible server architecture that can be easily customised, maintained and updated so as to enable adaptation of the data centre. Open server architecture will enable integration of computing resources with constrained thermal power dissipation such as embedded CPUs, GPUs, FPGAs, manycore processors integrated using established standards such as COM Express. - [Pillar 2] Advanced management strategies [Pillar 2a] and system efficiency enhancements (SEE) [Pillar 2b] will improve the behaviour of the system during runtime. The server architecture will include built-in enhancements (e.g., for computing acceleration, energy efficiency, dependability and security, behaviour monitoring, etc.) on system level. - [Pillar 3] Well-defined interfaces to surrounding software ecosystem will allow for an easy integration into existing data centre management solutions through the use of the latest middleware software for resource management, provisioning, etc. The results of these three pillars will be combined to produce TCO (Total Cost of Ownership)-optimized appliances, deployed in a real data centre environment and seamlessly interacting with existing infrastructure to run real-life applications.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 4.82M | Year: 2016

The projects principal aim is the development of UniServer: a universal system architecture and software ecosystem for servers. UniServer will facilitate the evolution of the Internet from an infrastructure where data is aggregated to centralized data-centres to an infrastructure where data are handled in a distributed and localized manner close to the data sources. UniServer will realize its bold goal by greatly improving the energy efficiency, performance, dependability and security of the current state-of-the-art micro-servers, while reinforcing the supported system software. UniServer will develop effective means to expose the intrinsic hardware heterogeneity caused by process variations, harness it and use it to its advantage for improving energy efficiency or performance. Lightweight, only software, mechanisms will be embedded for exposing to the system software the pessimistic voltage/frequency margins currently adopted in commercial processor and memory, which will be enhanced with new margin/fault-aware runtime and resource management policies. The UniServer technology will be ported on the world-first 64-bit ARM based Server-on-Chip and evaluated using smart emerging applications deployed in classical cloud business data-centres as well as in new environments closer to the data sources. UniServer aspires to deliver a unique fully working prototype that will turn the opportunities in the emerging Big Data and IoT markets into real, smarter products that can improve the everyday life and lead to a substantial financial and employment growth. The unique blend of expertise of UniServers consortium consisting of world leading low-power processor and Server-on-Chip suppliers (ARM, APM) as well as system software developer (IBM), and a set of emerging application drivers and established research organisations guarantees the successful realization of the ambitious goals, while reinforcing Europes strong position in traditional and new multi-billion euro market.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-01-2016 | Award Amount: 8.59M | Year: 2016

The Bonseyes project aims to develop a platform consisting of a Data Marketplace, Deep Learning Toolbox, and Developer Reference Platforms for organizations wanting to adopt Artificial Intelligence in low power IoT devices (edge computing), embedded computing systems, or data center servers (cloud computing). It will bring about orders of magnitude improvements in efficiency, performance, reliability, security, and productivity in the design and programming of Systems of Artificial Intelligence that incorporate Smart Cyber Physical Systems while solving a chicken-egg problem for organizations who lack access to Data and Models. Its open software architecture will facilitate adoption of the whole concept on a wider scale. It aims to address one of the most significant trends in the Internet of Things which is the shifting balance between edge computing and cloud computing. The early days of the IoT have been characterized by the critical role of cloud platforms as application enablers. Intelligent systems have largely relied on the cloud level for their intelligence, and the actual devices of which they consist have been relatively unsophisticated. This old premise is currently being shaken up, as the computing capabilities on the edge level advance faster than those of the cloud level. This paradigm shiftfrom the connected device paradigm to the intelligent device paradigm opens up numerous opportunities. To evaluate the effectiveness, technical feasibility, and to quantify the real-world improvements in efficiency, security, performance, effort and cost of adding AI to products and services using the Bonseyes platform, four complementary demonstrators will be built: Automotive Intelligent Safety, Automotive Cognitive Computing, Consumer Emotional Virtual Agent, and Healthcare Patient Monitoring. Bonseyes platform capabilities are aimed at being aligned with the European FI-PPP activities and take advantage of its flagship project FIWARE.

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