Entity

Time filter

Source Type

San Jose, CA, United States

Aptina Imaging Corporation is a company that sells CMOS imaging products. Aptina's products can be found in mobile phones, digital, and video cameras, notebook computers, surveillance cameras, and medical, automotive and industrial applications, as well as videoconferencing, barcode scanners, toys and gaming products.CMOS sensors from Aptina are used in Nikon V1 , Nikon J1, Nikon V2.According to a marketing report, in 2009 year Aptina had a 16% share of the CMOS image sensors market, with revenue estimated at $671 million. Wikipedia.


Patent
Aptina | Date: 2014-05-20

Systems and methods are provided for an adjustable filter engine. In particular, an electronic system is provided that can include a focus module, memory, and control circuitry. In some embodiments, the focus module can include an adjustable filter engine and a motor. By using the adjustable filter engine to generate a filter with a large number of filter coefficients, the control circuitry can accommodate a variety of system characteristics. For example, by generating a set of cumulative coefficients and re-arranging the order of the cumulative coefficients, the control circuitry can reduce the bit-width requirements of the adjustable filter engine hardware. For instance, the control circuitry can reduce the number of multipliers required to perform a convolution between an updated filter and one or more input signals. In some embodiments, the updated filter can be generated to reduce oscillations of the motor movement due to a new position request.


An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n type doped implant may be formed in the opening. Image lag is prevented by placing a p type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array.


Patent
Aptina | Date: 2014-08-20

An image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a semiconductor substrate. Buried light shielding structures may be formed on the substrate to prevent pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. The buried light shields may be formed over conductive gate structures. A metal silicide layer may be formed to completely cover these conductive gate structures. Antireflective coating material may optionally be formed over the metal silicide layer. Forming gate structures with a metal silicide liner can help reduce optical pixel crosstalk and enhance global shutter efficiency.


Patent
Aptina | Date: 2014-05-27

An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns.


Electronic devices may include image sensors that capture interleaved images having rows of long-exposure pixel values interleaved with rows of short-exposure pixel values. Processing circuitry in the electronic device may (spatially) partition the interleaved images into multiple bins. The processing circuitry may generate a weighted long-exposure pixel value for each bin and a weighted short-exposure pixel value for each bin. The weighted long and short exposure values in each bin may be combined to generate a binned high-dynamic-range (HDR) pixel value for that bin. The processing circuitry may output a binned HDR image formed from the binned HDR pixel values to additional circuitry such as video processing circuitry for performing additional image processing operations. If desired, the image sensor and processing circuitry may be combined into an integrated structure that generates a single binned HDR pixel value and multiple integrated structures may be used.

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