Entity

Time filter

Source Type

Austin, TX, United States

Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2016

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to enable smaller chargers, power factor convertors and switches in applications ranging from small applications such as implanted pace-makers, mobile-phones, computer to large applications such as automobile, machinery to very large applications such as ships, locomotives, traditional and renewable energy power plants. While the impact of the power switching product to be developed using this technology in this phase II project is broad, the use of this thin crystalline technology can have even broader impact across all modern semiconductor devices such as LED, PV, flexible CMOS and passive devices. The project will potentially enable thin form-factor packages in this broad range of power electronics applications. This Small Business Innovation Research (SBIR) Phase I project addresses challenges to further scaling of power MOSFETs which are one of the key building blocks of the electronic revolution we have witnessed over the last few decades. While the feature size of transistors has been constantly shrinking, the substrate thickness has been increasing. These substrates are currently mechanically thinned to minimize the negative impact of this increased thickness on performance and form-factor. There are significant challenges to continue this trend and the thin crystalline technology and device architecture proposed here can enable continued scaling of device metrics over the next decade with favorable cost structures. This effort will focus on the following specific technical challenges to bring it to market. (1) Develop power MOSFETs with improved switching characteristics using the thin crystalline technology (2) Develop the process technology on large area wafers used in current production lines (3) Develop the low-form factor package using the metallization features of thin-crystalline exfoliated technology (4) Characterize the device for performance and insertion into high volume de-risk (5) Develop a roadmap for a family of products that is sustainable over a decade to justify significant manufacturing investment to bring this technology to market.


Grant
Agency: Department of Defense | Branch: Army | Program: STTR | Phase: Phase I | Award Amount: 150.00K | Year: 2014

The objective of this proposal is to demonstrate the feasibility of producing large area, single crystal monolayer Molybdenum disulfide (MoS2) for high frequency applications. In order to be able to achieve this aim, it is necessary to work on three main components: (a) the channel material itself, (b) the gate dielectric and (c) the drain/ source contacts to the channel material. This work proposes to use optimization of chemical vapor deposition (CVD) growth parameters for obtaining large domain single layer MoS2 on device quality substrates, use of hexagonal Boron Nitride (h-BN) as a dielectric and its growth directly on Si-SiO2 to remove the need for any transfer before MoS2 growth and the use of highly conductive"defects"on the MoS2 surface to enhance charge injection in the metal- semiconductor interface.


Grant
Agency: Department of Defense | Branch: Army | Program: STTR | Phase: Phase II | Award Amount: 500.01K | Year: 2015

In Phase II we propose to optimize wafer scale MoS2 deposition process to fabricate uniform large area monolayer and multi-layer MoS2 films and analyze the defects on these films. Monolayer regions that can result in device periphery larger than 50m will be targeted. Further, the charge transfer doping process using TiOx will be optimized for MoS2 multi-layer and RF transistors will be fabrication on these multilayers. The device structure (geometry, length of underlap region, choice of gate dielectric, gate and contact materials) will be optimized to meet DC and RF performance targets of this solicitation. The transistors will be targeted to show an RF performance of fmax > 20GHz


Grant
Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 149.99K | Year: 2014

This Small Business Innovation Research (SBIR) Phase I project aims to demonstrate a innovative device architecture (UT-FET: Ultra Thin Field Effect Transistor) for scaling of FinFET devices beyond the 14nm node. The outcome of this project will be a CMOS device that is scalable and reduce off-state leakage as well as minimize threshold voltage variation. This project will develop a process technology that is compatible with high volume manufacturing using industrial toolsets. The main objective for the phase 1 of the proposed SBIR project is to demonstrate prototype UT-FET devices using manufacturing-capable tools and processes. The UT-FET device architecture involves a novel means of isolation of the device that can reduce cost, reduce leakage and increase speed of electronics systems. In this phase 1 of the SBIR project, production capable tools and processes will be used to demonstrate scalability of the technology for volume manufacturing. Successful completion of this technology demonstration can allow insertion of this technology into the growing markets for low power mobile communications electronics.

The broader impact/commercial potential of this project will be address and overcome the current limits to scaling in low power electronic devices. Low power electronics devices use CMOS technologies and the scaling of these devices have been the driving force behind the communication revolution over the last two decades. Further scaling of these devices will enable faster communication, longer battery life and more energy efficient operation of electronics systems. Additionally in the process of developing and demonstrating this technology new scientific and technological understanding of using thin crystalline devices and the tools to manufacture them in high volume will enable other applications in energy, RF signal processing and power management.


Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 149.99K | Year: 2014

This Small Business Innovation Research (SBIR) Phase I project aims to demonstrate a innovative device architecture (UT-FET: Ultra Thin Field Effect Transistor) for scaling of FinFET devices beyond the 14nm node. The outcome of this project will be a CMOS device that is scalable and reduce off-state leakage as well as minimize threshold voltage variation. This project will develop a process technology that is compatible with high volume manufacturing using industrial toolsets. The main objective for the phase 1 of the proposed SBIR project is to demonstrate prototype UT-FET devices using manufacturing-capable tools and processes. The UT-FET device architecture involves a novel means of isolation of the device that can reduce cost, reduce leakage and increase speed of electronics systems. In this phase 1 of the SBIR project, production capable tools and processes will be used to demonstrate scalability of the technology for volume manufacturing. Successful completion of this technology demonstration can allow insertion of this technology into the growing markets for low power mobile communications electronics. The broader impact/commercial potential of this project will be address and overcome the current limits to scaling in low power electronic devices. Low power electronics devices use CMOS technologies and the scaling of these devices have been the driving force behind the communication revolution over the last two decades. Further scaling of these devices will enable faster communication, longer battery life and more energy efficient operation of electronics systems. Additionally in the process of developing and demonstrating this technology new scientific and technological understanding of using thin crystalline devices and the tools to manufacture them in high volume will enable other applications in energy, RF signal processing and power management.

Discover hidden collaborations