Sunnyvale, CA, United States
Sunnyvale, CA, United States

Applied Materials, Inc. is an American corporation that supplies equipment, services and software to enable the manufacture of semiconductor, flat panel display, Glass, WEB and solar (crystalline and thin film) products. The company is headquartered in Santa Clara, California in the Silicon Valley. Applied Materials creates and commercializes nanomanufacturing technology used in the production of semiconductor (integrated circuit) chips for electronic gear, flat panel displays for computers, smartphones and television, glass coatings for homes and buildings, web (flexible substrate) coatings for industry and photovoltaic solar cells and modules using both thin film and crystalline (wafer or bulk) photovoltaic technology. Wikipedia.


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Patent
Applied Materials | Date: 2016-10-05

An evaporator for evaporating a material onto a substrate is described. The evaporator includes a guiding means for guiding the material towards at least one opening nozzle. The guiding means includes a measurement outlet for a portion of the material. The evaporator further includes a first measurement system configured for generating a first signal correlated with a deposition rate of the evaporator and having a first detector positioned for being coated by the material and a second optical measurement system for generating a second signal correlated with the deposition rate of the evaporator and wherein the second signal is based on the portion of the material of the measurement outlet.


Patent
Applied Materials | Date: 2016-09-16

An apparatus for forming an object includes a platform to support the object. The platform includes a first support plate including first holes and a second support plate arranged below the first support plate and including second holes. The second support plate is movable relative to the first support plate between an aligned configuration and a misaligned configuration. The apparatus further includes a dispensing system overlying the support plate to dispense a powder over the top surface of the first support plate and an energy source to apply energy to the powder dispensed on the top surface of the first support plate to form a fused portion of the powder. In the aligned configuration, the first holes are aligned with the second holes such that unfused powder can pass through the first holes into the second holes. In the misaligned configuration, the first holes are misaligned with the second holes.


Patent
Applied Materials | Date: 2017-01-18

Thin film batteries (TFB) are fabricated by a process which eliminates and/or minimizes the use of shadow masks. A selective laser ablation process, where the laser patterning process removes a layer or stack of layers while leaving layer(s) below intact, is used to meet certain or all of the patterning requirements. For die patterning from the substrate side, where the laser beam passes through the substrate before reaching the deposited layers, a die patterning assistance layer, such as an amorphous silicon layer or a microcrystalline silicon layer, may be used to achieve thermal stress mismatch induced laser ablation, which greatly reduces the laser energy required to remove material.


A deposition source (100, 200, 300, 400) for coating a movable substrate (20) is described. The deposition source includes: a source housing (120) to be fixed to a process chamber in such a way that a substrate (20) can be moved past an open front side of the process chamber during deposition; a gas inlet (130) for introducing a process gas into a coating processing region (125) of the source housing; and an evacuation outlet (140) for removing the process gas from a pumping region of the source housing. An evacuation partition unit (150) is arranged between the coating processing region (125) and the pumping region (126) with at least one opening or with a plurality of openings (152) defining a process gas flow path (155) from the coating processing region (125) into the pumping region (126).


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: Cordis | Branch: H2020 | Program: IA | Phase: FoF-12-2015 | Award Amount: 6.34M | Year: 2015

The total EU electronics industry employs 20.5 million people, sales exceeding 1 trillion and includes 396,000 SMEs. It is a major contributor to EU GDP and its size continues to grow fueled by demand from consumers to many industries. Despite its many positive impacts, the industry also faces some challenges connected with the enormous quantity of raw materials that it needs for sustainability, the huge quantity of Waste Electrical, Electronics Equipment (WEEE) generated and the threat of competition from Asia. To sustain its growth, to manage the impact of WEEE and to face the competition from Asia, the industry needs innovations in key areas. One such area is the drive for ultra-miniaturisation/ultlra-functionality of equipment. The key current road block/limitation to achieving the goal of ultra-miniaturisation/functionality is how to increase the component density on the printed circuit board (PCB). This is currently limited by the availability of hyper fine pitch solder powder pastes. FineSol aims to deliver at first stage an integrated production line for solder particles with size 1-10 m and to formulate solder pastes containing these particles. Thus, by proper printing methods (e.g. screen and jet printing) the fabrication of PCBs with more than double component density will be achieved. Consequently, this would effectively enable more than a doubling of the functions available on electronic devices such as cell phones, satellite navigation systems, health devices etc. The successful completion of the FineSol project would lift the ultra-miniaturisation/functionality road block and also enable reduction in raw material usage, reduction in WEEE, reduction in pollution and associated health costs and also a major reduction in EU energy demand with all its indirect benefits for environment and society.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-18-2015 | Award Amount: 82.27M | Year: 2016

The goal of EnSO is to develop and consolidate a unique European ecosystem in the field of autonomous micro energy sources (AMES) supporting Electronic European industry to develop innovative products, in particular in IoT markets. In summary, EnSO multi-KET objectives are: Objective 1: demonstrate the competitiveness of EnSO energy solutions of the targeted Smart Society, Smart Health, and Smart Energy key applications Objective 2: disseminate EnSO energy solutions to foster the take-up of emerging markets. Objective 3: develop high reliability assembly technologies of shapeable micro batteries, energy harvester and power management building blocks Objective 4: Develop and demonstrate high density, low profile, shapeable, long life time, rechargeable micro battery product family. Objective 5: develop customizable smart recharge and energy harvesting enabling technologies for Autonomous Micro Energy Source AMES. Objective 6: demonstrate EnSO Pilot Line capability and investigate and assess the upscale of AMES manufacturing for competitive very high volume production. EnSO will bring to market innovative energy solutions inducing definitive differentiation to the electronic smart systems. Generic building block technologies will be customizable. EnSO manufacturing challenges will develop high throughput processes. The ENSo ecosystem will involve all the value chain from key materials and tools to many demonstrators in different fields of application. EnSO work scope addresses the market replication, demonstration and technological introduction activities of ECSEL Innovation Action work program. EnSO relates to several of the Strategic Thrusts of ECSEL MASP. EnSO innovations in terms of advanced materials, advanced equipment and multi-physics co-design of heterogeneous smart systems will contribute to the Semiconductor Process, Equipment and Materials thrust. The AMES will be a key enabling technology of Smart Energy key applications.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-15-2015 | Award Amount: 150.05M | Year: 2016

The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moores law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-06-2015 | Award Amount: 23.11M | Year: 2016

The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.

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