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Atsugi, Japan

Arayashiki Y.,Anritsu Devices | Kamizono T.,Anritsu Devices | Ohkubo Y.,Anritsu Devices | Matsumoto T.,Anritsu Devices | And 2 more authors.
IEICE Transactions on Electronics | Year: 2013

We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (GCPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers. Source


Arayashiki Y.,Anritsu Devices | Ohkubo Y.,Anritsu Devices | Matsumoto T.,Anritsu Devices | Amano Y.,Anritsu Devices | And 2 more authors.
IEICE Transactions on Electronics | Year: 2010

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-jum self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers. Source

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