Thoppay P.E.,Analog Technologies |
Dehollain C.,Ecole Polytechnique Federale de Lausanne |
Green M.M.,University of California at Irvine |
Declercq M.J.,Ecole Polytechnique Federale de Lausanne
IEEE Journal of Solid-State Circuits | Year: 2011
This paper describes a receiver system design for impulse-radio ultra-wideband (IR-UWB) that operates at two carrier frequencies-3.494 and 3.993 GHzwith a 10-Mbps data rate. To reduce the power consumption of the front-end amplifiers, a super-regenerative architecture is used. An integrated circuit, implemented in a CMOS 0.18-μm technology and operating with a 1.5-V power supply, exhibits energy consumption of 0.24 nJ/bit with a measured sensitivity of -66 and -61dBm at 3.494 and 3.993 GHz, respectively, with a BER of 10 -3. Also included on the integrated circuit is an automatic tuning circuit based on a digital phase-locked loop that is used to set the resonant frequency of the super-regenerative block. © 2011 IEEE. Source
Shimonomura K.,Ritsumeikan University |
Kameda S.,Osaka University |
Iwata A.,Analog Technologies |
Yagi T.,Osaka University
IEEE Transactions on Neural Networks | Year: 2011
A silicon retina is an intelligent vision sensor that can execute real-time image preprocessing by using a parallel analog circuit that mimics the structure of the neuronal circuits in the vertebrate retina. For enhancing the sensor's robustness to changes in illumination in a practical environment, we have designed and fabricated a silicon retina on the basis of a computational model of brightness constancy. The chip has a wide-dynamic-range and shows a constant response against changes in the illumination intensity. The photosensor in the present chip approximates logarithmic illumination-to-voltage transfer characteristics as a result of the application of a time-modulated reset voltage technique. Two types of image processing, namely, Laplacian-Gaussian-like spatial filtering and computing the frame difference, are carried out by using resistive networks and sample/hold circuits in the chip. As a result of these processings, the chip exhibits brightness constancy over a wide range of illumination. The chip is fabricated by using the 0.25-μm complementary metal-oxide semiconductor image sensor technology. The number of pixels is 64 × 64, and the power consumption is 32 mW at the frame rate of 30 fps. We show that our chip not only has a wide-dynamic-range but also shows a constant response to the changes in illumination. © 2006 IEEE. Source
Analog Technologies | Date: 2011-05-20
A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp.
Analog Technologies | Date: 2011-01-03
A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A variable current source produces a varying amount of current in response to the difference between the input signals. A voltage measurement means produce a measurement signal in response to the difference between the input signals. A correction means produces a correction signal in response to the measurement signal to produce an optimum coarse phase overshoot. A timing comparison means produces a timing signal in response to the difference between the input signals. A correction means produces a correction signal in response to the timing signal to produce an optimum coarse phase overshoot.
Analog Technologies | Date: 2011-08-26
A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function.