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Shanghai, China

Yang S.,Fudan University | Feng Y.,Fudan University | Hong Z.,Fudan University | Liu Y.,Analog Devices Shanghai Co.
Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics

A single power supply class I linear audio amplifier is implemented in SMIC 0.18 μm 3.3 V CMOS technology. To increase the efficiency of class AB, a new class I linear audio amplifier was designed and the efficiency is derived. The power convertor in class I changes the power supply voltage of class AB continuously according to the input signal level to decrease the voltage drop on power transistors. Variable gain signal processing circuit is designed to optimize the power dissipation of both PMOS and NMOS power transistors. The output stage is composed of two bridge-tied three-stage amplifiers to improve the THD. The measured THD+N is better than 0.45% when output power is lower than 270 mW with 8 Ω load and the maximum efficiency is 70%. When output power is lower than 100 mW, the efficiency is doubled comparing to class AB. The measured results verify the theory. Source

Yi S.,Tsinghua University | Li K.,Tsinghua University | Li F.,Analog Devices Shanghai Co. | Zhang Q.,Chongqing Changan Automobile Co.
Qiche Gongcheng/Automotive Engineering

With a technique of line-based image processing, a lane mark recognition method and a low-cost lane departure warning system (LDWS) are proposed in this paper. Through line-by-line feature extraction and classification, the operation efficiency is enhanced with required memory reduced. On this basis, a low-cost LDWS is designed by using digital camera and 400MHz DSP chip. With no video decoding circuit and extended memory, the hardware complexity of the system is effectively reduced while ensuring a good recognition rate of lane marking. For evaluating the recognition performance of the system, a testing scheme suitable for embedded systems is proposed to fulfill a hardware-in-the-loop test on the recognition performance of LDWS based on offline made sample data. The results show that the system can achieve a good recognition rate in typical operating conditions with high stability and real-time performance. Source

Li W.-Q.,Tongji University | Li W.-Q.,Analog Devices Shanghai Co. | Qiu Y.-M.,Tongji University | Wu G.,China Telecom | And 2 more authors.
Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology)

To effectively allocate the multiple optima of a multimodal model during parameter window selection in semiconductor manufacture field, NichePSO algorithm with properly constructed fitness function is introduced into the optima seeking process under the conditions of multimodal model and process control requirements. The NichePSO algorithm based on method presented in this paper is proven as an effective method for process parameter window selection by both production validation data and simulation results on standard one-dimensional and two-dimensional multimodal functions. Source

Li W.,Tongji University | Li W.,Analog Devices Shanghai Co. | Qiu Y.,Tongji University | Jin X.,Analog Devices Shanghai Co. | And 2 more authors.
Journal of Semiconductors

This paper studies the typical failure modes and failure mechanisms of non-wetting in an FCBGA (flip chip ball grid array) assembly. We have identified that the residual lead and tin oxide layer on the surface of the die bumps as the primary contributor to non-wetting between die bumps and substrate bumps during the chip-attach reflow process. Experiments with bump reflow parameters revealed that an optimized reflow dwell time and H 2 flow rate in the reflow oven can significantly reduce the amount of lead and tin oxides on the surface of the die bumps, thereby reducing the non-wetting failure rate by about 90%. Both failure analysis results and mass production data validate the non-wetting failure mechanisms identified by this study. As a result of the reflow process optimization, the failure rate associated with non-wetting is significantly reduced, which further saves manufacturing cost and increases capacity utilization. © 2012 Chinese Institute of Electronics. Source

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