Analog Design Center

Chongqing, China

Analog Design Center

Chongqing, China
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Huang X.,Analog Design Center | Huang W.,Analog Design Center | Zhong Y.,Analog Design Center | He Z.,Analog Design Center
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

A closed-loop controlled interface IC on the principle of force-balance for differential-capacitive sensor system is presented in this work. Signal buffer immune for the parasitic capacitors is introduced to reduce the signal attenuation. A novel PID compensation block is designed to enhance the stability of the system with extremely high gain for accuracy, which is realized with active feedback Op Amp different from that of the traditional fashions. The circuit is fabricated in the 4μm BiCMOS process with the active area of 2.06mm 2 (excluding the pads) which is cost-efficient for industrial and commercial applications. The interface circuit operates at ±5V power supply and consumes 23mW of power. It provides typical analog output scale of 100mV/g with full scale of ±30g typically, and total noise of 2.5mgrms through the frequency range of DC-160Hz. ©2010 IEEE.


Huang X.,State Key Laboratory of Electronic Thin Films and Integrated Devices | Huang X.,Analog Design Center | Shi J.,State Key Laboratory of Electronic Thin Films and Integrated Devices | Liu L.,State Key Laboratory of Electronic Thin Films and Integrated Devices | And 2 more authors.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2012

An input stage using Darlington configuration with a lateral PNP and a vertical PNP combination for operational amplifier (Op-Amp) is presented in this paper. The emitter degeneration resistors are added to enhance the slew rate of the amplifier. To decrease the input offset voltage, the base current traced compensation technique is used to balance and compensate the different current component between the two input current branches through the current mirrors. This input stage is fabricated with the standard bipolar process, and the typical input offset voltage of 1mV, temperature coefficient of input offset voltage is around 5μV/°C over -55°C to 125°C, slew rate of 9.2V/μs and low input bias current are achieved without any trimming techniques. © 2012 IEEE.


Gao W.Q.,Analog Design Center | Wan H.,Analog Design Center | Zhang J.,Analog Design Center | Yang P.,Analog Design Center | And 2 more authors.
Applied Mechanics and Materials | Year: 2014

A 16-bit multi-channel simultaneous sampling ADC of wide analog input was designed. This ADC had a maximum conversion rate of 250[kSPS]. The ADC was implemented in 0.6[um] 2P3M standard CMOS process+high voltage CMOS process. For ±10 [V]/10[kHz] sine analog input and 250[kSPS] sampling rate, the testing result of the ADC at room temperature is that INL is 1.7[LSB], SINAD is 85.3[dB], EFS-is 0.055[%FS], EFS+ is 0.039[%FS]. © (2014) Trans Tech Publications, Switzerland.


Huang X.,Analog Design Center | Shi J.,Analog Design Center | Liu L.,Analog Design Center | Luo J.,Analog Design Center | And 2 more authors.
Journal of Theoretical and Applied Information Technology | Year: 2012

A proposed under-voltage lockout of compensated temperature coefficient threshold voltage without comparator is presented in this paper. The circuit achieves stability of threshold voltage without utilizing extra band gap reference voltage source and voltage comparator. In the temperature range of from -40°C to +125°C, variation of only 30mV of the threshold voltage occurs. The under-voltage lockout circuit is designed and simulated with standard CMOS process with featured size of 0.6μm. © 2005 - 2012 JATIT & LLS. All rights reserved.


Huang X.,Analog Design Center | Liu L.,Analog Design Center | Huang W.,Analog Design Center | Liu F.,Analog Design Center | And 3 more authors.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 | Year: 2014

An ESD clamp protection structure with current mirror for capacitor boosting was proposed in this paper. For the power rail protection, silicon-control-rectifier (SCR) is a better choice than the BIGFET as main ESD clamp device, which can provide better ESD robustness with smaller area and lower leakage current. The area of protection structure is reduced further for the utility of capacitor boosting technique. The trigger performance of the power rail clamp device was verified in the commercial CMOS process with featured size of 0.18°m. The total area of 50°m×50°m was achieved. The failure phenomenon in the measurement was also discussed for further improvement in this paper. © 2014 IEEE.


Huang X.,Analog Design Center | Huang X.,State Key Laboratory of Electronic Thin Films and Integrated Devices | Huang W.,Analog Design Center | Liu L.,Analog Design Center | And 2 more authors.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2012

In this paper, a low power, high density and fully integrated CMOS receiver front-end with digital output for optical signal processing systems is presented. The circuit is composed of transimpedance amplifier for weak optical current detection, limiting amplifier for both linear and limiting amplifications, control circuits and the digital output interface. The front-end is powered by a single 3.3V power supply with the power supply current of 12mA. Measured with a photodiode, a sensitivity of 0.7μA was achieved. The channel isolation between 8 channels is considered during the period of circuit design, layout floor plan and measurement carefully. The digital output signal is compatible with TTL/CMOS logic interface which can reduce the size of system dramatically and is easy to use. The optical sensor receiver was fabricated with a commercial mixed-signal CMOS process with feature size of 0.6μm, taking silicon area of 1.91mm×1.01mm including bonding pads for 8 channels. © 2012 IEEE.


Luncai L.,Analog Design Center | Xiaozong H.,Analog Design Center | Wengang H.,Analog Design Center
Applied Mechanics and Materials | Year: 2013

A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in a low-cost standard CMOS process with 0.6μm featured size, taking area of 600μm×150μm excluding the bonding pads. © (2013) Trans Tech Publications, Switzerland.


Zhou X.,Analog Design Center | Xu J.,Analog Design Center | Guo A.,Analog Design Center | Su C.,Analog Design Center | Lei L.,Analog Design Center
WIT Transactions on Information and Communication Technologies | Year: 2014

A low power, high performance pipeline analog-to-digital converter (ADC) is proposed. The ADC samples at 100 MS/s and only dissipates 90 mW under 3 V power supply. It is fabricated in 0.35 μm CMOS process and occupies 2.53 mm2. The ADC delivers up to 59.8 dBc spur-free dynamic range (SFDR) and 58.13 dBc total harmonic distortion (THD) with 70.1 MHz cosine input on undersampling condition and can be used in various communication systems where undersampling are required. © 2014 WIT Press.


Liao W.,Analog Design Center | Lei L.C.,Analog Design Center | Zhou X.D.,Analog Design Center
Applied Mechanics and Materials | Year: 2014

This paper presents the advantage of behavior model. This is useful for the SOC fast verification. A 14 bit pipeline ADC is constructed with simulation of behavior model and the noise model. A comparison of result is illustrated, between the ideal 14 bit ADC behavior model and the 14 bit pipeline ADC with non-idealities. © (2014) Trans Tech Publications, Switzerland.

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