Entity

Time filter

Source Type

Seville, Spain

Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014 | Year: 2014

Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals. © 2014 IEEE. Source


Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 | Year: 2014

In this paper, the design of a XOR/XNOR gate for low-power cryptographic applications is presented. The proposed gate optimizes the SABL (Sense Amplifier Based Logic) gate, widely used in cryptocircuit implementations, by removing residual charge in the pull-down circuit and simplifying the pull-up. The resulting gate improves SABL in terms of area, power consumption, propagation delay and resilience against Differential Power Analysis (DPA) attacks. To demonstrate the gain in performances, both gates have been designed, physically implemented and experimentally characterized, in a 90nm TSMC technology. Experimental results show a reduction of 15% in area, 12% in power consumption, and 40% in delay in the proposed gate. To demonstrate the gain in security of the proposal, simulation-based DPA attacks have been performed on respective Kasumi Sbox9 implementations, being our proposal suitable for inmediate application in high-performance secure cryptographic applications. © 2014 IEEE. Source


Saez A.G.,University of Seville | Saez A.G.,Anafocus | Quero J.M.,University of Seville | Jerez M.A.,Institute of Space Technology
IEEE Sensors Journal | Year: 2016

This paper presents mathematical modeling and the physical implementation of an Earth sensor based on thermopile detectors, which has been developed for the Microsat mission. The model includes a behavior model of the sensor and the radiant balance between the sensor and the Earth. The implemented instrument employs a solid-state technology, simplifies the pointing method and signal processing stage, and uses a very compact electronic design. A sensor prototype has been designed and built for the accuracy and irradiation tests. The evaluation of the device has been performed through the use of a testbench that allows sensor performance parameters to be determined. The sensor has achieved the functional mission requirements. © 2015 IEEE. Source


Brox P.,Institute Microelectronica Of Seville Imse Cnmcsic | Castro-Ramirez J.,University of Seville | Castro-Ramirez J.,Anafocus | Martinez-Rodriguez M.C.,University of Seville | And 4 more authors.
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2013

This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation. © 2013 IEEE. Source


Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
IEEE Journal on Emerging and Selected Topics in Circuits and Systems | Year: 2014

Cryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal-oxide-semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals. © 2014 IEEE. Source

Discover hidden collaborations