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Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 | Year: 2014

In this paper, the design of a XOR/XNOR gate for low-power cryptographic applications is presented. The proposed gate optimizes the SABL (Sense Amplifier Based Logic) gate, widely used in cryptocircuit implementations, by removing residual charge in the pull-down circuit and simplifying the pull-up. The resulting gate improves SABL in terms of area, power consumption, propagation delay and resilience against Differential Power Analysis (DPA) attacks. To demonstrate the gain in performances, both gates have been designed, physically implemented and experimentally characterized, in a 90nm TSMC technology. Experimental results show a reduction of 15% in area, 12% in power consumption, and 40% in delay in the proposed gate. To demonstrate the gain in security of the proposal, simulation-based DPA attacks have been performed on respective Kasumi Sbox9 implementations, being our proposal suitable for inmediate application in high-performance secure cryptographic applications. © 2014 IEEE.


Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014 | Year: 2014

Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals. © 2014 IEEE.


Rodriguez-Vazquez A.,University of Seville | Rodriguez-Vazquez A.,Anafocus | Dominguez-Castro R.,University of Seville | Dominguez-Castro R.,Anafocus | And 2 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence highdynamic range signal acquisition. © 2010 Copyright SPIE - The International Society for Optical Engineering.


Brox P.,Institute Microelectronica Of Seville Imse Cnmcsic | Castro-Ramirez J.,University of Seville | Castro-Ramirez J.,Anafocus | Martinez-Rodriguez M.C.,University of Seville | And 4 more authors.
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2013

This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation. © 2013 IEEE.


Saez A.G.,University of Seville | Saez A.G.,Anafocus | Quero J.M.,University of Seville | Jerez M.A.,Institute of Space Technology
IEEE Sensors Journal | Year: 2016

This paper presents mathematical modeling and the physical implementation of an Earth sensor based on thermopile detectors, which has been developed for the Microsat mission. The model includes a behavior model of the sensor and the radiant balance between the sensor and the Earth. The implemented instrument employs a solid-state technology, simplifies the pointing method and signal processing stage, and uses a very compact electronic design. A sensor prototype has been designed and built for the accuracy and irradiation tests. The evaluation of the device has been performed through the use of a testbench that allows sensor performance parameters to be determined. The sensor has achieved the functional mission requirements. © 2015 IEEE.


Tena-Sanchez E.,University of Seville | Castro J.,Anafocus | Acosta A.J.,University of Seville
IEEE Journal on Emerging and Selected Topics in Circuits and Systems | Year: 2014

Cryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal-oxide-semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals. © 2014 IEEE.


Salas-Paracuellos L.,Anafocus | Alba L.,Anafocus | Villacorta-Atienza J.A.,Complutense University of Madrid | Makarov V.A.,Complutense University of Madrid
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

Animals for surviving have developed cognitive abilities allowing them an abstract representation of the environment. This internal representation (IR) may contain a huge amount of information concerning the evolution and interactions of the animal and its surroundings. The temporal information is needed for IRs of dynamic environments and is one of the most subtle points in its implementation as the information needed to generate the IR may eventually increase dramatically. Some recent studies have proposed the compaction of the spatiotemporal information into only space, leading to a stable structure suitable to be the base for complex cognitive processes in what has been called Compact Internal Representation (CIR). The Compact Internal Representation is especially suited to be implemented in autonomous robots as it provides global strategies for the interaction with real environments. This paper describes an FPGA implementation of a Causal Neural Network based on a modified FitzHugh-Nagumo neuron to generate a Compact Internal Representation of dynamic environments for roving robots, developed under the framework of SPARK and SPARK II European project, to avoid dynamic and static obstacles. © 2011 SPIE.


Salas-Paracuellos L.,Anafocus | Alba-Soto L.,Anafocus
Cognitive Systems Monographs | Year: 2014

Animals for surviving have developed cognitive abilities allowing them an abstract representation of the environment. This internal representation (IR) may contain a huge amount of information concerning the evolution and interactions of the animal and its surroundings. The temporal information is needed for Internal Representations of dynamic environments and is one of the most subtle points in its implementation as the information needed to generate the IR may eventually increase dramatically. Chapter 3 in the book proposed the compression of the spatiotemporal information into only space, leading to a stable structure suitable to be the base for complex cognitive processes in what has been called Compact Internal Representation (CIR). The Compact Internal Representation is especially suited to be implemented in autonomous robots as it provides global strategies for the inter­action with real environments. This chapter describes an FPGA implementation of a Causal Neural Network based on a modified FitzHugh-Nagumo neuron to generate a Compact Internal Representation of dynamic environments for roving robots to avoid dynamic and static obstacles. © Springer International Publishing Switzerland 2014.


Caballero-Garcia D.J.,Anafocus | Jimenez-Marrufo A.,Anafocus
Cognitive Systems Monographs | Year: 2014

The purpose of this chapter is to describe how different visual routines can be developed and embedded in the AnaFocus’ Eye-RIS Vision System on Chip (VSoC) to close the perception to action loop within the roving robots developed for the testing of the insect brain models. The Eye-RIS VSoC employs a bioinspired architecture where image acquisition and processing are intermingled and the processing itself is carried out in two steps.At the first step, processing is fully parallel owing to the concourse of dedicated circuit structures which are integrated close to the sensors. At the second step, processing is realized on digitally-coded information data by means of digital processors. The Eye-RIS VSoC systems provide with image-processing capabilities and speed comparable to high-end conventional vision systems without the need for high-density image memory and intensive digital processing. Current perceptual schemes are often based on information derived from visual routines. Since realworld images are quite complex to be processed for perceptual needs with traditional approaches,more computationally feasible algorithms are required to extract the desired features from the scene in real time, to efficiently proceed with the consequent action. In this chapter the development of such algorithms and their implementation taking full advantage of the sensing-processing capabilities of the Eye-RIS VSoC are described. © Springer International Publishing Switzerland 2014.


Jimenez-Marrufo A.,Anafocus | Caballero-Garcia D.J.,Anafocus
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

The purpose of the current paper is to describe how different visual routines can be developed and embedded in the AnaFocus' Eye-RIS Vision System on Chip (VSoC) to close the perception to action loop within the roving robots developed under the framework of SPARK II European project. The Eye-RIS Vision System on Chip employs a bio-inspired architecture where image acquisition and processing are truly intermingled and the processing itself is carried out in two steps. At the first step, processing is fully parallel owing to the concourse of dedicated circuit structures which are integrated close to the sensors. At the second step, processing is realized on digitally-coded information data by means of digital processors. All these capabilities make the Eye-RIS VSoC very suitable for the integration within small robots in general, and within the robots developed by the SPARK II project in particular. These systems provide with image-processing capabilities and speed comparable to high-end conventional vision systems without the need for high-density image memory and intensive digital processing. As far as perception is concerned, current perceptual schemes are often based on information derived from visual routines. Since real world images are quite complex to be processed for perceptual needs with traditional approaches, more computationally feasible algorithms are required to extract the desired features from the scene in real time, to efficiently proceed with the consequent action. In this paper the development of such algorithms and their implementation taking full advantage of the sensing-processing capabilities of the Eye-RIS VSoC are described. © 2011 SPIE.

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