Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 999.95K | Year: 2011
Existing silicon on insulator (SOI) pixel detectors which integrate single gate transistors with substrate diodes are limited by two key problems. First, the SOI transistor performance is degraded by the large potentials that must be applied to the substrate to fully deplete the diodes. Secondly, the performance of these SOI pixel detectors degrades with exposure to radiation due to charge trapping in the buried oxide. However, SOI pixel detectors offer the best resolution at high speed while using less power at lower cost than competing technologies like monolithic active pixel detectors or 3-D chip stacking. American Semiconductors next generation FlexPix SOI pixel detector technology provides all of the benefits of existing SOI pixel detectors, but eliminates the two key problems that limit performance. FlexPix combines multi-independent gate Flexfet transistors with diode detectors integrated in the substrate. Flexfets unique multi-gate architecture effectively shields the transistor channel and eliminates the performance degradation due to both substrate bias and radiation charge trapping. Feasibility of the next generation x-ray imager has been established by successful completion of the design, layout, simulation, and analysis using the FlexPix SOI pixel detector technology. All Phase I technical objectives were met or exceeded through the collaborative research effort between American Semiconductor and the Fermilab Particle Physics Division. American Semiconductor exceeded the program objections by also completing the design, layout and simulation of two FlexPix advanced characterization test chips that in Phase II will provide key detector data to facilitate future designs by other government and commercial groups and spur business growth in Phase III and beyond. Successful manufacture of the substrate diodes in the FlexPix technology was demonstrated in an earlier Phase I program. Fabrication and testing of two FlexPix wafer lots will enable iterative design and process optimization to meet the requirements of the MAMBO x-ray imaging application and provide detailed process information for future business development. The first manufacturing run will employ the multi-chip configuration completed in Phase I containing both the basic x-ray imager design and the two pixel characterization test chips. The second manufacturing run will allow for design and process optimization based upon testing from the first wafer lot. For the second wafer lot, the team will create a full-scale MAMBO FlexPix x-ray imager prototype that will provide a key demonstration of the technology to spur additional business development in Phase III. Commercial Applications and Other Benefits: The FlexPix technology will lead to improvements in pixel detectors used in medical, military, government and related commercial imaging applications. Specific applications include high dynamic range biomedical x-ray, nondestructive and non-invasive testing, health physics, and environmental studies.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.99K | Year: 2012
ABSTRACT: American Semiconductor will develop and demonstrate structural integration of a conformal load bearing antenna structure (CLAS). Future aircraft will incorporate distributed electronics, sensors, and flight control transducers directly into the composite airframe. For near-term Air Force applications, adding RF electronics into the CLAS will improve the performance of a wide variety of intelligence, surveillance, and reconnaissance (ISR), communication navigation identification (CNI), and electronic warfare (EW) functions. Longer term, embedding electronics into the airframe will enable"fly-by-feel"optimization of aircraft for increased performance, better fuel efficiency, and improved reliability. In Phase I, American Semiconductor will integrate a Flexible MEMS Reconfigurable Antenna with Low Noise Amplifier into a composite stack such as carbon fiber reinforced plastic. This CLAS prototype includes a flexible electronic system composed of RF devices, active components and multi-level circuitry and will be analyzed for both mechanical and electrical performance. In Phases II and III, American Semiconductor will expand the program to incorporate large area, flexible CMOS digital circuits on polymer substrates suitable for flexible, autonomous micro-sensor integration. Combining high-performance flexible CMOS with the RF and substrates created in Phase I will allow for creation of complete, complex CLAS devices suitable for numerous Air Force missions. BENEFIT: The technology developed and proven in this SBIR has multiple benefits, starting with the immediate application of conformal load bearing antennas (CLAS) but continuing into other conformal, pliable, and/or structural electronics and ultimately into industrial applications and consumer devices. CLAS, by definition, integrates the antenna function into the structure in such a way that the antenna itself is a load bearing structure to improve gain, reduce drag, reduce system size and weight, and enable new system concepts. CLAS provides lightweight and cost effective solutions to very large aperture requirements, enables high performance radar capability on smaller vehicles, and lowers drag and weight to improve platform endurance and speed. The technology in this SBIR can also be extended to fly-by-feel applications for active sensing of the flight environment. Fly-by-feel vastly improves empirical models for control and analytical modeling for design, enables exploitation of phenomena that cannot be analyzed accurately, allows a reduction in factors of safety due to load uncertainty, and reduction in air vehicle certification time and cost. The direct benefit of this work is that Phase II will deliver a complete, functional prototype Flexible MEMS Reconfigurable Antenna (FMRA) in a CLAS. This effort will result in not only a working FMRA, but will also demonstrate a proven manufacturing capability for additional applications such as the fly-by-feel wing with integrated sensors and high performance distributed computing. The technology in this SBIR extends into military, commercial and industrial markets such as pliable smart sensor systems, wearable electronics embedded into garments, and foldable/roll-able electronics such as phones, tablets, and e-readers. Phase I of this project is the first step in creating truly pliable electronic devices. Thinness and pliability are desirable features for many portable electronics with obvious benefits including reduced size, reduced weight, increased durability, and the potential for new functionality based on flexibility. As products become thinner, they flex due to a loss of mechanical rigidity. Deformation during use results in cracking and failure of traditional integrated circuits. If an e-book, mobile phone or other product could be built in fully flexible high performance electronics technology, then the resulting device would achieve the ultimate thinness and be very durable. When this concept is taken to its logical extreme, the devices become bendable, rollable and foldable. This also provides a new basis for products yet to be envisioned or proposed. Military applications include soldier-worn electronics that greatly benefit from improvements in size, weight, and durability that come with pliable circuits. The medical communities have interest in flexible electronics for patient worn and patient portable devices for preventative, pre-treatment, treatment, and post-treatment monitoring. The commercialization potential is far larger than necessary for success in the flexible electronics space.
American Semiconductor, Inc. | Date: 2011-02-28
Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase I | Award Amount: 99.96K | Year: 2011
The goal of this project is to develop an ultra low power (ULP), radiation hardened, reconfigurable analog-to-digital converter (ADC) in the 130nm Flexfet Independently Double Gated SOI CMOS process. Satellites include a large number of sensors which perform both generic system functions and specific mission needs. For these various sensors, the required resolution for the associated ADC may be as low as 8-bits or as high as 22-bits while the bandwidth can range from a few kHz to several MHz. A new Hybrid Pipelined Delta-Sigma (HPDS) ADC will be developed as this particular hybrid architecture shows great promise with regards to programmability, reconfigurability, and radiation-immunity. Similarly, American Semiconductor"s Flexfet process is ideally suited for the design of rad-hard ULP, reconfigurable circuits. Flexfet transistors provide a wide range of dynamic threshold voltage adjustment which supports dynamic reconfigurability and performance tuning. The Flexfet technology provides an innovative solution for superior environmental characteristics to meet temperature and radiation tolerance requirements with ability to fine tune the power and performance for high levels of integration like a microprocessor. Implementing the HPDS ADC architecture in the Flexfet technology will provide a superior ADC solution for the unique requirements and environmental challenges of multi-year space missions.
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase I | Award Amount: 99.92K | Year: 2009
The is an effort to increase radiation hardness/survivability of microelectronics through innovation of production processes and capabilities by establishing an economically viable low-volume sub-65nm rad-hard foundry CMOS capability based on Digital Beam Processing (DBP) technology. American Semiconductor (ASI) and Digibeam Corporation (DBC) propose a collaboration to evaluate sub-65nm radiation-hardened Flexfet™ CMOS realized in resistless, direct-write, DBP. This project will determine feasibility for CMOS integration of DBP as a supply solution for Ballistic Missile Defense System (BMDS) requirements. This SBIR includes both technical and economic analysis. DBP integration and sub-65nm Flexfet feasibility are evaluated using optical proximity test cells manufactured by integrating a DBP process step into a CMOS fabrication sequence. DBP will be applied to ASI’s existing design files, fabricated, and evaluated with ASI’s advanced metrology capability. DBP evaluation data will be used as input to sub-65nm Flexfet simulations. This project includes a scope typically beyond Phase I funding but that is feasible due to ASI’s unique low-volume foundry capability. Work includes: (1) Fabrication, simulation and modeling of DBP test cells, (2) DBP comparison to traditional photolithography, (3) Economic and technical evaluation including assessment of technical readiness (4) Determination of feasibility with cost model for radiation-hardened sub-65nm Flexfet DBP CMOS.