Boise, ID, United States

American Semiconductor, Inc.

www.allamerican.com
Boise, ID, United States

All American Semiconductor, Inc. is an electronic components distributor based in Miami, FL. The company filed for bankruptcy and has sold virtually all assets.All American Semiconductor, LLC has re-emerged as the new All American. Wikipedia.


Time filter

Source Type

Patent
American Semiconductor, Inc. | Date: 2011-02-28

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F^(2). The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.


Patent
American Semiconductor, Inc. | Date: 2011-02-28

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F^(2). Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 999.95K | Year: 2011

Existing silicon on insulator (SOI) pixel detectors which integrate single gate transistors with substrate diodes are limited by two key problems. First, the SOI transistor performance is degraded by the large potentials that must be applied to the substrate to fully deplete the diodes. Secondly, the performance of these SOI pixel detectors degrades with exposure to radiation due to charge trapping in the buried oxide. However, SOI pixel detectors offer the best resolution at high speed while using less power at lower cost than competing technologies like monolithic active pixel detectors or 3-D chip stacking. American Semiconductors next generation FlexPix SOI pixel detector technology provides all of the benefits of existing SOI pixel detectors, but eliminates the two key problems that limit performance. FlexPix combines multi-independent gate Flexfet transistors with diode detectors integrated in the substrate. Flexfets unique multi-gate architecture effectively shields the transistor channel and eliminates the performance degradation due to both substrate bias and radiation charge trapping. Feasibility of the next generation x-ray imager has been established by successful completion of the design, layout, simulation, and analysis using the FlexPix SOI pixel detector technology. All Phase I technical objectives were met or exceeded through the collaborative research effort between American Semiconductor and the Fermilab Particle Physics Division. American Semiconductor exceeded the program objections by also completing the design, layout and simulation of two FlexPix advanced characterization test chips that in Phase II will provide key detector data to facilitate future designs by other government and commercial groups and spur business growth in Phase III and beyond. Successful manufacture of the substrate diodes in the FlexPix technology was demonstrated in an earlier Phase I program. Fabrication and testing of two FlexPix wafer lots will enable iterative design and process optimization to meet the requirements of the MAMBO x-ray imaging application and provide detailed process information for future business development. The first manufacturing run will employ the multi-chip configuration completed in Phase I containing both the basic x-ray imager design and the two pixel characterization test chips. The second manufacturing run will allow for design and process optimization based upon testing from the first wafer lot. For the second wafer lot, the team will create a full-scale MAMBO FlexPix x-ray imager prototype that will provide a key demonstration of the technology to spur additional business development in Phase III. Commercial Applications and Other Benefits: The FlexPix technology will lead to improvements in pixel detectors used in medical, military, government and related commercial imaging applications. Specific applications include high dynamic range biomedical x-ray, nondestructive and non-invasive testing, health physics, and environmental studies.


Grant
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase I | Award Amount: 99.96K | Year: 2011

The goal of this project is to develop an ultra low power (ULP), radiation hardened, reconfigurable analog-to-digital converter (ADC) in the 130nm Flexfet Independently Double Gated SOI CMOS process. Satellites include a large number of sensors which perform both generic system functions and specific mission needs. For these various sensors, the required resolution for the associated ADC may be as low as 8-bits or as high as 22-bits while the bandwidth can range from a few kHz to several MHz. A new Hybrid Pipelined Delta-Sigma (HPDS) ADC will be developed as this particular hybrid architecture shows great promise with regards to programmability, reconfigurability, and radiation-immunity. Similarly, American Semiconductor"s Flexfet process is ideally suited for the design of rad-hard ULP, reconfigurable circuits. Flexfet transistors provide a wide range of dynamic threshold voltage adjustment which supports dynamic reconfigurability and performance tuning. The Flexfet technology provides an innovative solution for superior environmental characteristics to meet temperature and radiation tolerance requirements with ability to fine tune the power and performance for high levels of integration like a microprocessor. Implementing the HPDS ADC architecture in the Flexfet technology will provide a superior ADC solution for the unique requirements and environmental challenges of multi-year space missions.


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 149.98K | Year: 2013

Reliable, readily-manufacturable technologies are needed to create the next generation of high-density, high-functionality 3D integrated circuits (ICs) for integrating silicon pixel detectors with CMOS read-out ICs. Current methods for 3D IC development are severely limited by the thickness of the CMOS wafers and the restrictions that result due to the diameter of the through-silicon vias (TSVs) that connect the chips together. The thinner these CMOS wafers can be made, the smaller the TSV diameter and the more efficient the TSVs become which will in-turn improve the performance of the silicon pixel detectors and other products that are enhanced by 3D integration. American Semiconductor proposes modifying its existing FleX process to support 3D integration of CMOS ICs and silicon pixel detectors. American Semiconductor has demonstrated the revolutionary FleX process for creating flexible, ultra-thin, single- crystalline CMOS with multi-layer metal interconnect. FleX is a post-fab process that can be applied to any SOI CMOS wafer and delivers fully functional, flexible wafers with a final silicon thickness of & lt;200nm. In Phase I, American Semiconductors FleX process will be enhanced to demonstrate 3D chip stacking including manufacture of the TSVs and will immediately demonstrate feasibility for deep sub- micron TSVs. In Phase II, the TSVs will be optimized, metal interconnect layers will be added, and multiple chip stacks will be demonstrated. Successful demonstration and commercialization of FleX 3D ICs will benefit DoE by supporting creation of future generations of silicon pixel detectors for use in nuclear and high-energy physics. In the commercial markets, improved 3D chip stacking methods will provide benefits to high-performance computing, cell phones, and CMOS imagers. Current methods for 3D IC development are limited by the thickness of the CMOS wafers and the resulting dimensions of the TSVs that connect the layers together. The thinner these CMOS wafers can be made, the smaller and more efficient the through-silicon vias become which will in-turn improve the performance of silicon pixel detectors for DoE and commercial applications. In Phase I, American Semiconductors FleX process for creating flexible, ultra-thin ( & lt;200nm), single-crystalline CMOS will be enhanced to demonstrate 3D chip stacking including manufacture of through-silicon vias (TSVs). In Phase II, the TSVs will be optimized, metal interconnect will be added, and multiple chip stacks will be demonstrated. Commercial Applications and Other Benefits: The FleX 3D chip stacking process is applicable to numerous commercial applications including 3D integration of high performance logic with high density memory. The technology provides the opportunity to integrate technologies based on different materials such as III-V and silicon while maintaining the capability to fabricated sophisticated layers post bonding.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.99K | Year: 2012

ABSTRACT: American Semiconductor will develop and demonstrate structural integration of a conformal load bearing antenna structure (CLAS). Future aircraft will incorporate distributed electronics, sensors, and flight control transducers directly into the composite airframe. For near-term Air Force applications, adding RF electronics into the CLAS will improve the performance of a wide variety of intelligence, surveillance, and reconnaissance (ISR), communication navigation identification (CNI), and electronic warfare (EW) functions. Longer term, embedding electronics into the airframe will enable"fly-by-feel"optimization of aircraft for increased performance, better fuel efficiency, and improved reliability. In Phase I, American Semiconductor will integrate a Flexible MEMS Reconfigurable Antenna with Low Noise Amplifier into a composite stack such as carbon fiber reinforced plastic. This CLAS prototype includes a flexible electronic system composed of RF devices, active components and multi-level circuitry and will be analyzed for both mechanical and electrical performance. In Phases II and III, American Semiconductor will expand the program to incorporate large area, flexible CMOS digital circuits on polymer substrates suitable for flexible, autonomous micro-sensor integration. Combining high-performance flexible CMOS with the RF and substrates created in Phase I will allow for creation of complete, complex CLAS devices suitable for numerous Air Force missions. BENEFIT: The technology developed and proven in this SBIR has multiple benefits, starting with the immediate application of conformal load bearing antennas (CLAS) but continuing into other conformal, pliable, and/or structural electronics and ultimately into industrial applications and consumer devices. CLAS, by definition, integrates the antenna function into the structure in such a way that the antenna itself is a load bearing structure to improve gain, reduce drag, reduce system size and weight, and enable new system concepts. CLAS provides lightweight and cost effective solutions to very large aperture requirements, enables high performance radar capability on smaller vehicles, and lowers drag and weight to improve platform endurance and speed. The technology in this SBIR can also be extended to fly-by-feel applications for active sensing of the flight environment. Fly-by-feel vastly improves empirical models for control and analytical modeling for design, enables exploitation of phenomena that cannot be analyzed accurately, allows a reduction in factors of safety due to load uncertainty, and reduction in air vehicle certification time and cost. The direct benefit of this work is that Phase II will deliver a complete, functional prototype Flexible MEMS Reconfigurable Antenna (FMRA) in a CLAS. This effort will result in not only a working FMRA, but will also demonstrate a proven manufacturing capability for additional applications such as the fly-by-feel wing with integrated sensors and high performance distributed computing. The technology in this SBIR extends into military, commercial and industrial markets such as pliable smart sensor systems, wearable electronics embedded into garments, and foldable/roll-able electronics such as phones, tablets, and e-readers. Phase I of this project is the first step in creating truly pliable electronic devices. Thinness and pliability are desirable features for many portable electronics with obvious benefits including reduced size, reduced weight, increased durability, and the potential for new functionality based on flexibility. As products become thinner, they flex due to a loss of mechanical rigidity. Deformation during use results in cracking and failure of traditional integrated circuits. If an e-book, mobile phone or other product could be built in fully flexible high performance electronics technology, then the resulting device would achieve the ultimate thinness and be very durable. When this concept is taken to its logical extreme, the devices become bendable, rollable and foldable. This also provides a new basis for products yet to be envisioned or proposed. Military applications include soldier-worn electronics that greatly benefit from improvements in size, weight, and durability that come with pliable circuits. The medical communities have interest in flexible electronics for patient worn and patient portable devices for preventative, pre-treatment, treatment, and post-treatment monitoring. The commercialization potential is far larger than necessary for success in the flexible electronics space.


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 124.93K | Year: 2012

The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low manufacturing cost associated with a structured ASIC. The low cost, high performance customization of the structured ASIC portion of the chip is made possible by the 1-D 45 nm Mask-Lite process technology. The chip architecture is optimized for sensor data handling applications in space and the design process provides for a short development schedule. The architecture provides a hard macro microcontroller core with via-ROM program memory, SRAM data memory, CPU support logic, an appropriate set of analog functions, and a structured ASIC section for application specific functionality. A rad-hard by design logic cell library is provided for the structured ASIC area of the die along with a number of pre-compiled macro functions such as timers and serial I/O to reduce development time. The 1-D Mask-Lite process provides a dramatic reduction in the mask cost, allowing lower volume designs to gain access to 45 nm technology, and provides performance improvement over conventional via mask structured ASIC technologies by eliminating metal layer stubs. Standard logic design, verification and layout EDA tools are used to complete a chip design. The fixed microcontroller platform portion of the chip is implemented with optimized standard cells rather than the structured ASIC logic cells, resulting in standard ASIC performance levels for the core logic.


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 99.97K | Year: 2010

Improvements in silicon-on-insulator (SOI) technology have resulted in development of monolithic chip designs for radiation image sensors and particle detectors by facilitating the use of the handle silicon layer for the detectors and the SOI layer for the readout circuits. Unfortunately, even the most advanced SOI-based imagers are still limited in effectiveness due to threshold (Vt) shifts when bias voltages are applied to fully deplete the handle silicon for detector performance. The required bias voltage range causes severe shifts in the Vt of the CMOS transistors of the readout circuitry. Flexfet SOI


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2014

ABSTRACT: Emergence and feasibility for flexible body-worn electronics and particularly medical patches requires high performance electronics capability. The problem is that these new technologies must have flexible and conformal physical formats and conventional electronic components are not in any way flexible. In the CLAS Phase I program, a new flexible high-performance manufacturing and materials system was demonstrated for feasibility. This system included high performance components integrated with printed substrates and printed antennas to support data processing and wireless communications in a flexible and conformal format. FleX silicon-on-polymer integrated circuits and printed devices such as the antenna demonstrated in the CLAS Phase I program have provided a feasible solution for flexible electronics and wireless applications. This Phase II will build on the Flexible Hybrid System (FHS) technology proven in the CLAS Phase I and will apply the technology to body-worn and bio-sensor applications. The output of this Phase II will be the manufacturing and materials methods required for producing this technology. The program includes the demonstration of the new capability with the production of FHS development kits that can be utilized to enable a wide variety of programs that demand high performance flexible electronics. The program includes an applied demonstration of the new capability by integrating an advanced printed ammonia biosensor on completed development kits. BENEFIT: BENEFITS Manufacturing capability for CLAS and other distributed sensor defense applications. Development Kits that can be used by sensor/product teams developing body-worn electronics. Establishment of U.S. manufacturing capability at the leading edge of flexible electronics. Development of new flexible electronics assembly capability and technology. Development of new flexible electronics materials. COMMERCIAL APPLICATIONS Major commercial products companies desire to introduce ultra-thin and flexible consumer and medical electronics to the market. This includes products with flexible OLED displays, body-worn sensors, smart clothing with wireless communication and the conversion of a number of common devices such as tablets and cell phones to flexible versions. The technology in this Phase II is enabling for all of these applications.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.37K | Year: 2011

ABSTRACT: The Space Plug-and-play Avionics (SPA) initiative is designed to improve the ability of the US military to respond to rapidly changing operational needs by creating, integrating, and launching a new spacecraft in less than one week. This would provide major benefits to war fighters on the ground, in the sky, and at sea. SPA-1 ASICs using I2C as the transport interface will likely be the most proliferated endpoint for connection to the satellites"many sensors and actuators. Thus, the implementation of the SPA-1 ASIC must minimize size, weight and power without sacrificing performance. In Phase I, American Semiconductor demonstrated the ability to meet these needs by designing a high performance 50MHz, ultra low power, radiation-hardened SPA-1 ASIC processor core in the 130nm Flexfet double gate CMOS process. Operating at 0.5V, the Flexfet microprocessor core provides a 3X improvement in power over conventional bulk CMOS and a nearly 10X improvement in performance. In Phase II, American Semiconductor will design, manufacture and test Flexfet SPA-1 ASICs. This Phase II program will also provide an ASIC development platform and silicon proven building blocks for creation of other ultra low power, radiation-hardened ASICs in a US wafer foundry for use by DoD prime contractors. BENEFIT: There is a clear military requirement and desire for the technology to be developed under this Phase II SBIR. Space has become a contested environment in which it is critical for the US to have a clear technology advantages. The Space Plug-and-play Avionics (SPA) initiative is part of the Operationally Responsive Space goal of reducing the time from identification of a mission need to fielding an operationally capable satellite. The importance of the SPA initiative was recently recognized by being named the 2010 Hot Technology Contest Winner for the Air Force. In addition, AFRL has sponsored a number of SPA programs and a key driver in the development of the SPA standards. For the Air Force to fully benefit from the SPA initiative, new microelectronics that implement the SPA protocols and standards must be developed to address the low power, high performance and radiation tolerance requirements of space. SPA-x ASICs are fundamental building blocks for development of these plug-and-play satellites. SPA-1 uses the I2C transfer protocol and is envisioned by satellite designers as the"leaves on the tree", or most numerous SPA ASIM component, for connection to the multiple sensors and actuators employed on the plug-and-play satellites. The current start-of-the-art for SPA-1 is implementation in a structured ASIC. A structured ASIC is a good approach for development, but cannot meet the low power and performance specifications or mixed-signal capability developed in this program. Dramatic breakthroughs in the area of low power electronics is crucial for continued advancement in radiation-hardened electronics for space and military applications. Under this SBIR Phase II program, American Semiconductor will deliver SPA-1 ASICs built in the 130nm Flexfet CMOS technology to significantly reduce the size, weight, and power when compared to using the existing structured ASIC implementation. Operating at 0.5V, a SPA-1 ASIC in the double-gate Flexfet CMOS technology will provide a 3X improvement in power over conventional bulk CMOS and a nearly 10X improvement in performance while also providing inherent tolerance to radiation. The power and performance breakthroughs to be demonstrated under this proposal are also needed across a wide spectrum of commercial applications that include medical, distributed networks, and energy scavenging sensors, to name just a few. This approach must be successfully commercialized to insure technology availability to defense programs, provide a stable supply base, and benefit from on-going development to sustain the technology. American Semiconductor has a demonstrated track record supplying and supporting new technology as demonstrated by the company"s selection as the 2007 Supplier of the Year Award for Technology from Boeing Corp. The commercialization potential for this SBIR is along two paths. The first commercialization opportunity from this proposal will be to market the Flexfet SPA-1 ASIC to both military and commercial satellite manufacturers. Success of the Flexfet SPA-1 prototype will lead to development of more complex SPA-x variants such as the SPA-U USB and SPA-S Spacewire variants. The second path is providing the Flexfet ULP CMOS process as a foundry offering to satellite and IC designers that need to conserve system power. This has multiple sub-areas of commercialization such as foundry wafer sales, IP block licensing, and follow-on derivative product development and sales. Along the second commercialization path, the first product to leverage the technology from this SBIR will be IP blocks in Flexfet CMOS complementary to the SPA-1 ASIM, such as SRAM, ADCs, and I2C interface. These IP blocks allow designers to immediately utilize Flexfet CMOS to design ULP ICs that can further size, weight, and power (SWaP) advantages in satellite and other low power systems. Success in this area will enable further development of IP blocks, which leads to faster, lower cost development of future ICs through the use of IP blocks proven in silicon and available to designers working with Flexfet. The technology from this proposal will require little additional funding to bring to market. Flexfet CMOS is in place and being used by customers today. The SPA-1 ASIC developed in this program is anticipated to meet datasheet requirements such that silicon can be immediately started to fulfill customer demand for initial development. Qualification and reliability testing for both commercial terrestrial and military space applications can proceed in parallel with delivery of initial prototypes. Marketing and advertising expense will be necessary, but will leverage existing company efforts as much as possible.

Loading American Semiconductor, Inc. collaborators
Loading American Semiconductor, Inc. collaborators