Time filter

Source Type

Albany, NY, United States

Carcasi M.,Tokyo Electron | Bassett D.,Tokyo Electron | Printz W.,Tokyo Electron | Kawakami S.,America LLC | Miyata Y.,Tokyo Electron
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2012

Line pattern collapse (LPC) becomes a critical concern as integrated circuit fabrication continues to advance towards the 22 nm node and below. Tokyo Electron Limited (TEL) has been investigating LPC mitigation methods for many years [1]. These mitigation methods include surfactant rinses to help reduce surface tension and Laplace pressures forces that accompany traditional DIW rinses. However, the ability to explore LPC mitigation techniques at EUV dimensions is experimentally limited by the cost and availability of EUV exposures. With this in mind, TEL has adopted a combined experimental and simulation approach to further explore LPC mitigation methods. Several analytical models have been proposed [2, 3, 4] for a LPC simulation approach. However, the analytical models based on Euler beam theory are limited in the complexity of profile and material assumptions. Euler beam based models are also now questionable because they are outside the beam theory's intended aspect ratio regime [5]. The authors explore the use of finite element models in addition to Euler beam theory based models to understand resist collapse under typical EUV patterning conditions. The versatility of current finite element techniques allows for exploration of resist material property effects, profile and geometry effects, surface versus bulk modulus effects, and rinse and surfactant rinse effects. This paper will discuss pattern-collapse trends and offers critical learning from this simulation approach combined with experimental results from an EUV exposure system and TEL CLEAN TRACK ACT TM 12 platform, utilizing state of the art collapse mitigation methods. © 2012 SPIE. Source

Patil S.,America LLC
Technical Paper - Society of Manufacturing Engineers | Year: 2014

The evolution of press drive systems can be directly tied to the changing trends in part requirements throughout many manufacturing segments. With each type of stamping press drive system comes an attempt to solve manufacturing concerns such as continual tightening of part tolerances, the introduction of new materials, including high-strength steels and advanced high-strength steels, as well as the ever-present push toward increasing production efficiency. This presentation covers hydraulic, eccentric, link, and servo presses, their general characteristics, features, and benefits, and how integrating these types of presses into a production system affects users' ability to address the above concerns. Source

Petrillo K.,SEMATECH | Huang G.,SEMATECH | Ashworth D.,SEMATECH | Georger J.,SEMATECH | And 7 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2011

Line width roughness (LWR) control is a critical issue in extreme ultraviolet lithography (EUVL). The difficulty of controlling LWR and the need to minimize it have grown as the sensitivity of materials and resolution in the resist patterning process has improved. Another critical feature that has become difficult to control in EUVL and 22nm half-pitch systems is pattern collapse. The increase of aspect ratio that comes from further scaling promotes the onset of pattern collapse. Both pattern collapse and LWR are easily observed in EUVL and leading-edge ArF immersion lithography. This paper will demonstrate recent gains in LWR control in leading EUV films using track-based processes, etch-based improvements, and the results of combined techniques. Also the use of a newly developed EUV-specific FIRM™ rinse chemistry to reduce pattern collapse will be discussed along with future development activities and industry requirements for both LWR and pattern collapse. © 2011 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE). Source

Clark R.D.,America LLC
Materials | Year: 2014

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. © 2014 by the authors. Source

Bhuyian M.N.U.,New Jersey Institute of Technology | Poddar S.,Heritage Institute of Technology | Misra D.,New Jersey Institute of Technology | Tapily K.,America LLC | And 5 more authors.
Applied Physics Letters | Year: 2015

This work evaluates the defects in HfZrO as a function of Zr addition into HfO2 and when the dielectric was subjected to a slot-plane-antenna (SPA) plasma treatment in a cyclic process to form TiN/HfZrO/SiON/Si gate stacks. The defect energy levels, estimated by temperature-dependent current-voltage measurements, suggest that Zr addition in HfO2 modifies the charge state of the oxygen vacancy formation, V+. The influence of electron affinity variation of Hf and Zr ions on the charged oxygen vacancy levels seems to have contributed to the increase in defect activation energy, Ea, from 0.32 eV to 0.4 eV. The cyclic SPA plasma exposure further reduces the oxygen vacancy formation because of the film densification. When the dielectric was subjected to a constant voltage stress, the charge state oxygen vacancy formation changes to V2+ and improvement was eliminated. The trap assisted tunneling behavior, as observed by the stress induced leakage current characteristics, further supports the oxygen vacancy formation model. © 2015 AIP Publishing LLC. Source

Discover hidden collaborations