San Jose, CA, United States
San Jose, CA, United States

Altera Corporation is a Silicon Valley manufacturer of Programmable Logic Devices , reconfigurable complex digital circuits. The company released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions. Wikipedia.


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A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.


A controller for a power converter formed with a plurality of converter stages, and method of operating the same. In one embodiment, the controller includes a power system controller configured to determine an unequal current allocation among the plurality of converter stages based on an operation of the power converter. The controller also includes a converter stage controller configured to control an output current produced by each of the plurality of converter stages in response to the current allocation.


Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.


A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.


In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.


Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. Systems and methods are also provided herein for authentication mechanisms that require more than one data cycle to complete.


An integrated circuit for detecting and correcting error events associated with atomic particles includes error detection circuitry connected to monitoring circuitry. The error detection circuitry may include a particle sensing circuit (e.g., a diode circuit) embedded below a substrate surface of the integrated circuit, and a particle validation circuit (e.g., a sense amplifier) coupled to the particle sensing circuit through a conductive via. The particle sensing circuit may detect and collect stray charges generated by an atomic particle passing through the integrated circuit. A particle validation circuit may generate an output signal that is indicative of the particle energy of the atomic particle based on the collected stray charge by the particle sensing circuit. Monitoring circuitry may identify the particle energy based on the output signal and subsequently generate an error correction signal, which activates error correction operations in the integrated circuit.


Patent
Altera | Date: 2017-03-08

Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.


One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies (106-1, 106-2). On the first semiconductor die (106-1) in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge (108) to a second semiconductor die (106-2). Another embodiment relates to a method of data communication between at least two in-package semiconductor dies (106-1, 106-2). A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die (106-1). The analog signal is transmitted through a silicon bridge (108) to a second semiconductor die (106-2). Other embodiments, aspects and features are also disclosed.


Grant
Agency: GTR | Branch: EPSRC | Program: | Phase: Research Grant | Award Amount: 567.20K | Year: 2016

Energy efficiency is one of the primary design constraints for modern processing systems. Hardware accelerators are seen as a key technology to address the high performance with limited energy issue. In addition the arrival of computing languages such as OpenCL offer a route to the programmer to target different types of multi-core accelerators using a single source code. Performance portability is a significant challenge specially if the accelerators have different microarchitectures such as is the case in CPU-GPU-FPGA systems. This research addresses the energy and performance challenge by investigating how a device formed by processing units with different granularities ranging from coarse grain CPU cores of different complexity, medium grain general purpose GPU cores and fine grain FPGA logic cells can be dynamically programmed. The challenge is to be able to program all these resources with a single programming model and create a run-time system that can automatically tune the software to the best execution resource from energy and performance points of view. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?

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