San Jose, CA, United States
San Jose, CA, United States

Altera Corporation is a Silicon Valley manufacturer of Programmable Logic Devices , reconfigurable complex digital circuits. The company released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions. Wikipedia.

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An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second subchannels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.


Integrated circuits with guard rings are provided. Integrated circuits may include functional circuitry that is sensitive to random noise sources. The functional circuitry may be formed using nonplanar transistor devices such as FinFET devices. A nonplanar guard ring may be provided that help isolate the functional circuitry from the interfering noise sources. The nonplanar guard ring may include edges that are formed using long rectangular strips of diffusion regions and/or smaller interleaved L-shaped diffusion regions. At least two columns of multiple interlocking pairs of L-shaped diffusion regions or at least one column of staggered L-shaped diffusion regions can be formed along an edge of the nonplanar guard ring to help ensure proper noise leakage protection between adjacent L-shaped diffusion regions along that edge.


Methods for control block size reduction through intellectual property (IP) migration in an integrated circuit (IC) device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The IP construction data may contain instruction sets for implementing logical operations of a controller-based IP core in a core region of the IC device. Such data creates flexibility to configure the controller-based IP core in the core logic circuit as a soft IP core, when required. In this scenario, the controller-based IP core can be removed from the controller of the IC device during device fabrication. As a result, the footprint (e.g., area) of the controller of the IC device can be reduced, which subsequently increases cost-savings for the IC fabrication.


A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.


Patent
Altera | Date: 2017-03-08

Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.


One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies (106-1, 106-2). On the first semiconductor die (106-1) in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge (108) to a second semiconductor die (106-2). Another embodiment relates to a method of data communication between at least two in-package semiconductor dies (106-1, 106-2). A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die (106-1). The analog signal is transmitted through a silicon bridge (108) to a second semiconductor die (106-2). Other embodiments, aspects and features are also disclosed.


Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data may be stored in a storage circuit. For the purpose of implementing the circuit design in an integrated circuit, a decoding circuit may retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of the decompression operation with the base configuration data to restore the configuration data. The restored configuration data may serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.


An integrated circuit for detecting and correcting error events associated with atomic particles includes error detection circuitry connected to monitoring circuitry. The error detection circuitry may include a particle sensing circuit (e.g., a diode circuit) embedded below a substrate surface of the integrated circuit, and a particle validation circuit (e.g., a sense amplifier) coupled to the particle sensing circuit through a conductive via. The particle sensing circuit may detect and collect stray charges generated by an atomic particle passing through the integrated circuit. A particle validation circuit may generate an output signal that is indicative of the particle energy of the atomic particle based on the collected stray charge by the particle sensing circuit. Monitoring circuitry may identify the particle energy based on the output signal and subsequently generate an error correction signal, which activates error correction operations in the integrated circuit.


In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.


Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. Systems and methods are also provided herein for authentication mechanisms that require more than one data cycle to complete.

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