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Kouassi S.,University of Tours | Gautier G.,University of Tours | Thery J.,CEA Grenoble | Desplobain S.,University of Tours | And 3 more authors.
Journal of Power Sources | Year: 2012

Since the 90's, porous silicon has been studied and implemented in many devices, especially in MEMS technology. In this article, we present a new approach to build miniaturized proton exchange membrane micro-fuel cells using porous silicon as a hydrogen diffusion layer. In particular, we propose an innovative process to build micro fuel cells from a "corrugated iron like" 3D structured porous silicon substrates. This structure is able to increase up to 40% the cell area keeping a constant footprint on the silicon wafer. We propose here a process route to perform electrochemically 3D porous gas diffusion layers and to deposit fuel cell active layers on such substrates. The prototype peak power performance was measured to be 90 mW cm -2 in a "breathing configuration" at room temperature. These performances are less than expected if we compare with a reference 2D micro fuel cell. Actually, the active layer deposition processes are not fully optimized but this prototype demonstrates the feasibility of these 3D devices. © 2012 Elsevier B.V.


Grant
Agency: European Commission | Branch: FP7 | Program: CP-IP | Phase: NMP-2007-3.5-2 | Award Amount: 9.03M | Year: 2008

Various emerging markets in the field of non silicon multimaterial micro devices offer a huge potential for commercialisation in the near future. However, solutions for mass-production for most of them have still to be developed. The objective of the MULTILAYER project is to develop a set of solutions for the large-scale production of micro devices based on a technology we call Rolled multi material layered 3D shaping technology and using the concept of tape casting and advanced printing techniques. This technology will enable to manufacture complex multifunctional 3D-micro parts on a layer by layer manner and in a high-throughput context. Each layer can be given a specific structure. They will be printed and contain channels and cavities that are open or filled in a very high precision manner. The microsystems will have as basic building material ceramics, which is a clear advantage in applications that require high temperature, corrosive environments and long time reliability. Furthermore, it will allow spatial resolutions under 10 m and the ceramics tapes developed will be down to 10 m thin. The Rolled multi material layered 3D shaping technology will have several advantages: - it will be an efficient mass production method - the fabrication series can attain over a million units - it will offer a good flexibility for a wide variety possible component designs, - it will allow the integration of different materials as different layers enabling to manufacture multimaterial multilayered packages with a high degree of integration, - the process will be very reliable, indeed, every single layer can be advantageously inspected and controled


Vitiello J.,Altatech
Solid State Technology | Year: 2011

Phase-change memory (PCM) emerged as one of the potential candidates for next-generation nonvolatile memory applications. The technology was based on fast and reversible phase-change effects in chalcogenide materials, causing them to switch between crystalline and amorphous states. Equipment supplier, Altatech Semiconductor used its pulsed liquid-precursor, metalorganic CVD (MOCVD) technology to fill confined areas in PCM devices, working in a project jointly with STMicroelectronics, CEA-LETI, and the CNRS-LTM laboratory in Grenoble, France. The AltaCVD tool was used to create bilayer GeTe films by applying Ge and Te as liquid precursors under the project. Thin-film characterization was performed using x-ray photoelectron spectroscopy (XPS) measurements in 'quasi' in situ mode.


A nanotopographic measuring device comprises an input arranged to receive sets of measurement data relating to a semi-conductor wafer (20) and memory organised into first and second working tables and a results table. A calculation function is capable of establishing a current surface equation from localised gradient values. The equation is established in such a way as to generally minimise a deviation amount between the gradient values calculated from the current surface equation and the localised gradient values. A reconstruction function calculates localised gradient values from a set of measurement data corresponding to an area of the wafer, and completes the working tables with these values. It repeatedly calls the calculation function, each time with a part of the values of the first working table and the second working table corresponding to a portion of the area of the wafer to determine, each time, a current surface equation. It completes the results table with the localised height data corresponding to this area, in relation to the reference plane of the wafer, said localised height data being calculated from at least certain of the current surface equations.


Patent
Altatech | Date: 2011-07-11

The reactor includes: a chamber having a lower wall, an upper wall and a sidewall connecting the lower wall to the upper wall; a support plate mounted inside the chamber; at least one first supply line for a first gas, and at least one separate second supply line for a second gas; a gas injection device; and a gas collector. The gas injection device includes at least one injector connected to the first supply line and at least one injector connected to the second supply line, the injectors leading into the chamber through at least one inlet provided in the sidewall; all of the injectors of the first supply line and all of the injectors of the second supply line are connected one above the other; and the collector includes at least one outlet in the sidewall, opposite the inlet relative to the support plate, and substantially at the inlet.


Patent
Altatech | Date: 2013-03-08

The invention relates to a method for manufacturing a semiconductor wafer including a conductive via extending from a main surface of the wafer, said the via having a shape factor greater than five, the wafer including a dielectric layer, the method including: producing, by means of deep etching, at least one recess in the semiconductor wafer, the recess extending from the main surface of the wafer and having a shape factor greater than five, the recess including a side surface; forming at least one dielectric layer in the recess, including two treatments in a controlled-pressure reactor, one of said the treatments including the chemical vapor deposition, at sub-atmospheric pressure, of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a temperature lower than 400 C. and at a pressure greater than 100 Torr in the reactor, and another of the treatments including the plasma-enhanced chemical vapor deposition of a dielectric onto the side surface of the recess, the chemical deposition being carried out at a pressure of less than 20 Torr in the reactor; and filling the recess with a conductive material, thus forming a via.


Patent
Altatech | Date: 2012-10-09

The invention relates to a dark-field semi-conductor wafer inspection device including, in the following order, a light source for emitting an incident beam to a wafer along a first axis, a concentrator (7) that is symmetrical in relation to a plane passing through the first and second axes and is provided with a mirror that is elliptically cut along a plane perpendicular to an axis perpendicular to the first axis and has a generator parallel to the first axis, parallel first and second slits (13, 14) being set up side-ways in first and second portions (9, 10) of the concentrator at the points for concentrating the light that is scattered by the wafer and reflected by the second and first portions of the concentrator, respectively, and a photomultiplier using a slit.


Patent
Altatech | Date: 2014-02-21

A reactor device for chemical vapor deposition includes a reaction chamber having a side wall and a substrate stand having a peripheral surface and a main surface facing a reactive gas injector, the injector and said surface defining a work space therebetween. The substrate stand is arranged in the reaction chamber such as to form an annular passage between the peripheral surface of the substrate stand and the side wall of the reaction chamber. A system for discharging gases is in fluid connection with the reaction chamber. A purge gas injector includes an injection channel leading into the reaction chamber through an annular opening. A laminar flow of purge gas is injected through the annular opening and flows in said annular passage to an opening.


Patent
Altatech | Date: 2014-02-21

A reactor device for chemical vapor deposition comprises a reaction chamber having a purge gas inlet. A gas discharge channel is linked to said reaction chamber via a circumferential opening in the inner wall of said chamber. The reaction chamber is arranged such that a purge gas stream flows from the purge gas inlet to the discharge channel. Said inner wall of the reaction chamber comprises means for exchanging heat with the purge gas, for example fins.


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