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Vallett D.,PeakSource Analytical LLC | Gaudestad J.,Neocera LLC | Richardson C.,Allied High Technology Products Inc.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2014

Magnetic current imaging (MCI) using superconducting quantum interference device (SQUID) and giant-magneto-resistive (GMR) sensors is an effective method for localizing defects and current paths [1]. The spatial resolution (and sensitivity) of MCI is improved significantly when the sensor is as close as possible to the current paths and associated magnetic fields of interest. This is accomplished in part by nondestructive removal of any intervening passive layers (e.g. silicon) in the sample. This paper will present a die backside contour-milling process resulting in an edge-to-edge remaining silicon thickness (RST) of < 5 microns, followed by a backside GMR-based MCI measurement performed directly on the ultra-thin silicon surface. The dramatic improvement in resolving current paths in an ESD protect circuit is shown as is nanometer scale resolution of a current density peak due to a power supply short-circuit defect at the edge of a flip-chip packaged die. Copyright © 2014 ASM International® All rights reserved.

Stevie F.A.,North Carolina State University | Garcia R.,North Carolina State University | Richardson C.,Allied High Technology Products Inc. | Zhou C.,North Carolina State University
Surface and Interface Analysis | Year: 2014

Depth profiling SIMS analysis to determine diffusion of an element from a surface layer into a substrate or penetration of a species through a barrier layer can be very difficult to achieve because one cannot readily detect a trace amount of an element after depth profiling through a matrix level of the same element. Removal of the substrate and analysis from the back of the sample has provided a solution to this problem. Substrate removal methods have been either mechanical polish followed by a chemical etch or mechanical polish alone. The latter method has provided successful results for a wide range of studies including penetration of Cu though a barrier material, diffusion from high-k dielectric layers, and site specific analysis on a product wafer. In order to make the polishing method more routine and reduce the time required, substrate removal was investigated with use of a milling machine designed to de-process packaged semiconductor devices. Initial work on an Si substrate shows residual Si less than 100 nm could be obtained in a region that was subsequently analyzed with good depth resolution in a SIMS depth profile. Mesa sample preparation with this instrument was also demonstrated. Copyright © 2014 John Wiley & Sons, Ltd.

Richardson C.,Allied High Technology Products Inc. | Liechty G.,Allied High Technology Products Inc. | Smith C.,Allied High Technology Products Inc. | Karow M.,Allied High Technology Products Inc.
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2013

Utilizing existing sample preparation techniques and/or toolsets in the typical failure analysis lab is an effective way of reducing the bottlenecks on higher-demand contour milling machines. Methodologies for faster milling on contouring machines, and use of a through-silicon measurement tool (used for measuring remaining silicon thickness), will demonstrate how to achieve higher throughput in the lab while preserving or reintroducing the device bows/warps that were present at the start. © 2013 IEEE.

Wei M.S.,AMD Inc | Chong H.B.,AMD Inc | Lim S.H.,AMD Inc | Richardson C.,Allied High Technology Products Inc.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2014

High resolution laser imaging, using high numerical aperture (NA) solid immersion lens (SIL) for backside fault isolation imposes stringent sample preparation requirements; as a result of the short focal length of SIL, a die must be thinned to a targeted thickness with less than a ±5 μm silicon thickness variation across the entire die. Flip chip packaged dice suffer from warpage due to various package sizes and substrate thicknesses. Such broad spectrums of part geometries pose a great challenge to meet such silicon planarity requirements. As relaxation of the packaged silicon during polishing causes the warpage profile to change dynamically and unpredictably throughout the thinning process, it has become an added challenge to meet the stringent sample preparation requirements. To overcome the stochastic nature of this problem, a two-step polishing recipe consisting of computer numerical control (CNC) mechanical milling and polishing processes has been developed to achieve sufficient silicon thickness uniformity to enable SIL imaging across an entire silicon chip as large as approximately 20 mm × 15 mm. Copyright © 2014 ASM International® All rights reserved.

Abraham IV G.K.,Allied High Technology Products Inc.
Metallography, Microstructure, and Analysis | Year: 2013

This study addresses the affect of mounting material used with an encapsulated metallographic specimen on its Rockwell hardness test results. Thirty-five specimens were sectioned from a grade 1144 medium carbon steel rod as the experimental material. Thirty of the sections were encapsulated in six different mounting materials (the test groups), and five were left unencapsulated (the control group). Each specimen was ground and polished using the same metallographic preparation procedure, and then hardness tests were performed using the Rockwell hardness C scale. The repeatability (r PB) value, from the ASTM International Inter-Laboratory Study to Establish Precision Statements for ASTM E18, was used to compare the hardness test results of the encapsulated test groups to the results of the unencapsulated control group. Using that study, if the average hardness of a test group fell within ± r PB of the control group, there would be approximately a 95 % probability that it was equivalent to the control group. Five out of the six test groups (all except transparent thermoplastic) had average hardness values that fell within ±r PB of the control group average. Four of the six test groups (all except green phenolic and transparent thermoplastic) had standard deviations that were less than r PB. With such results, green phenolic and transparent thermoplastic are not suitable mounting materials for Rockwell hardness testing. © 2013 Springer Science+Business Media New York and ASM International.

Richardson C.,Allied High Technology Products Inc.
Electronic Device Failure Analysis | Year: 2014

As demonstrated in this paper, achieving a uniform RST to within ±5 μm is possible when a system that is capable of mapping and thinning silicon to its dynamic contour is used.

Allied High Technology Products Inc. | Date: 2013-10-21

Countertop CNC (Computer Numerically Controlled) precision machining center.

Richardson C.,Allied High Technology Products Inc. | Liechty G.,Allied High Technology Products Inc. | Smith C.,Allied High Technology Products Inc. | Karow M.,Allied High Technology Products Inc.
Microelectronics Reliability | Year: 2013

Electrical failure analysis toolsets continue to develop at a pace significantly faster than sample preparation techniques. New solid immersion lenses (SIL) have been developed that require tighter requirements in remaining silicon thickness (RST) variation. Due to the SIL requirements, well established sample preparation techniques are quickly becoming ineffective, and new techniques/tools are required. In this paper, we will present a new methodology for preparing contoured devices by utilizing a contour capable milling system with an incorporated spectral reflectance measurement tool to enable contour correction milling based on remaining silicon thickness. This technique has demonstrated the capability of meeting 50 μm (or other desired target thickness) ±5 μm remaining silicon thickness requirement as requested by the SIL manufacturers. © 2013 Elsevier Ltd. All rights reserved.

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