Santa Clara, CA, United States

Alliance Semiconductor

www.alsc.com
Santa Clara, CA, United States

Alliance Semiconductor Corporation designs and manufactures memory and memory-intensive logic. Alliance's product lines include Static Random Access Memory , Pseudo SRAM , Dynamic Random Access Memory , Flash Memory, and embedded memory and logic solutions. For a little while they also sold some video chipsets for PCs. Founded in 1985, Alliance is headquartered in Santa Clara, California, with design centers in Santa Clara, as well as Hyderabad and Bangalore, India. Wikipedia.


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A memory-access completion notification associated with a data unit is received from a thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. The processing status is updated to indicate that the data unit has not been processed by any thread. The updated processing status is written into the window buffer.


A memory access request associated with a data unit is received from a first thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. It is determined whether the data unit is being processed by a second thread. If so, a rejection procedure is performed to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory). Otherwise, an acknowledgement procedure is performed to grant the first thread to access the attribute value associated with the data unit from/to the DRAM.


Patent
Alliance Semiconductor | Date: 2017-05-17

A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.


Patent
Alliance Semiconductor | Date: 2017-02-03

A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.


An electronic device includes functional modules, gates, monitor module, signal control module and record module. The functional modules are operated on clock signal for generating request instruction and response signal. The gate is coupled to the functional modules for transmitting request instruction and response signal to functional module on enable signals. The monitor module is coupled to the functional modules and the gates for generating hold signal. The monitor module generates enable signals on finish signal. The clock signal control module coupled to the functional modules and the monitor module for outputs main clock signal to generate clock signals. The clock signal control module generates record instruction and stop clock signals, and the clock signal control module re-outputs clock signals on finish signal. The record module coupled to the functional modules and the clock signal control module begins to record request instruction and response signal when receiving record instruction.


A system and method of performing speculative parallel execution of a cache line unaligned load instruction including speculatively predicting whether a load instruction is unaligned with a cache memory, marking the load instruction as unaligned and issuing the instruction to a scheduler, dispatching the unaligned load instruction in parallel to first and second load pipelines, determining corresponding addresses for both load pipelines to retrieve data from first and second cache lines incorporating the target load data, and merging the data retrieved from both load pipelines. Prediction may be based on matching an instruction pointer of a previous iteration of the load instruction that was qualified as actually unaligned. Prediction may be further based on using a last address and a skip stride to predict a data stride between consecutive iterations of the load instruction. The addresses for both loads are selected to incorporate the target load data.


A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.


Patent
Alliance Semiconductor | Date: 2017-07-19

A graphics processing system and power gating method thereof, the graphics processing system (100) comprising: a graphics processing unit (GPU) (130), a bus interface (110) and a power management unit (PMU) (120), the GPU comprising a control unit (140) and a plurality of partitions (151-154); the method includes: when the bus interface receives an external graphics command, utilizing the PMU to turn on a power supply of the control circuit (S210); subsequently utilizing the control circuit to turn on power supplies of one or more partitions of the plurality of partitions corresponding to the external graphics command (S220); when then control circuit detects any one of the plurality of partitions is in an idle state, utilizing the control circuit to turn off the power supply of the partition in the idle state (S230); when the bus interface detects the plurality of partitions are in a full idle state, utilizing the bus interface to turn off the power supply of the control circuit via the PMU (S240); and when the PMU turns off the power supply of the control circuit, the control circuit may also turn off the power supplies of the plurality of the partitions.


Patent
Alliance Semiconductor | Date: 2017-07-26

Provided are a system and method for dynamically adjusting a voltage frequency, the system comprising: an operational unit, a power management unit; a hard-ware activity monitoring unit for monitoring an operation state and temperature information of the operational unit, and determining, according to the operation state, temperature information, an a previous adjustment result, whether the operation voltage and operation frequency of the operational unit need to be updated, and when it is determined to update the operation voltage and operation frequency, generating a first control signal to the power management unit to adjust the operation voltage and operation frequency; and a hardware voltage monitoring unit for detecting time sequence information of the operational unit, and determining whether to fine-tune the operation voltage according to the time sequence information, and when it is determined to fine-tune the operation voltage, generating a second control signal to the power management unit to fine-tune the operation voltage.


Patent
Alliance Semiconductor | Date: 2017-04-14

A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a supply voltage to an adjustment signal according to the first signal and the second signal, and a fourth transmission gate, coupling the inverse of the adjustment signal to a ground according to the first signal and the second signal.

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