Santa Clara, CA, United States

Alliance Semiconductor

www.alsc.com
Santa Clara, CA, United States

Alliance Semiconductor Corporation designs and manufactures memory and memory-intensive logic. Alliance's product lines include Static Random Access Memory , Pseudo SRAM , Dynamic Random Access Memory , Flash Memory, and embedded memory and logic solutions. For a little while they also sold some video chipsets for PCs. Founded in 1985, Alliance is headquartered in Santa Clara, California, with design centers in Santa Clara, as well as Hyderabad and Bangalore, India. Wikipedia.

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A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.


A memory-access completion notification associated with a data unit is received from a thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. The processing status is updated to indicate that the data unit has not been processed by any thread. The updated processing status is written into the window buffer.


A memory access request associated with a data unit is received from a first thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. It is determined whether the data unit is being processed by a second thread. If so, a rejection procedure is performed to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory). Otherwise, an acknowledgement procedure is performed to grant the first thread to access the attribute value associated with the data unit from/to the DRAM.


A first request is received from a window checker, requesting to read cell data from a window buffer or write cell data into the window buffer, where the first request contains at least first cell index. A second request is received from a window releaser, requesting to read cell data from the window buffer or write cell data into the window buffer, where the second request contains at least second cell index. A register stores the first cell index, the second cell index, a first lock flag indicating whether the window checker has read cell data but hasnt written cell data back and a second lock flag indicating whether the window releaser has read cell data but hasnt written cell data back. One of the requests is granted according to the first and second cell indices and the first and second lock flags.


Patent
Alliance Semiconductor | Date: 2017-05-17

A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.


Patent
Alliance Semiconductor | Date: 2017-03-08

A power-control device for generating and controlling a supply voltage (Vsupply) is provided. The power-control device includes a variant delay chain (1000) with a delay length, a sampling circuit (1001), a comparison circuit (1002), and a power manager (101). The variant delay chain (1000) receives an initial signal (S1003) and performs a delay operation on the initial signal (S1003) according to the delay length to generate a delay signal (S1000). The sampling circuit (1001) receives the delay signal (S1000) and performs a sampling operation on the delay signal (S 1000) to generate a sampled signal (S1001). The comparison circuit (1002) receives the sampled signal (S1001) and compares the sampled signal (S1001) with a reference signal (S1004) to generate a comparison result signal (S1002). The power manager (101) receives the comparison result signal (S1002) and adjusts the supply voltage (Vsupply) according to the comparison result signal (S1002).


Patent
Alliance Semiconductor | Date: 2017-03-29

A microprocessor with a fused reservation stations (RS) structure including a primary RS, a secondary RS, and a bypass system. The primary RS has an input for receiving issued instructions, has a push output for pushing the issued instructions to the secondary RS, and has at least one bypass output for dispatching issued instructions that are ready for dispatch. The secondary RS has an input coupled to the push output of the primary RS and has at least one dispatch output. The bypass system selects between the bypass output of the primary RS and at least one dispatch output of the secondary RS for dispatching selected issued instructions. The primary and secondary RS may each be selected from different RS structure types. A unify RS provides a suitable primary RS, and the secondary RS may include multiple queues. The bypass output enables direct dispatch from the primary RS.


Patent
Alliance Semiconductor | Date: 2017-01-04

A graphics processing unit and associated graphics processing method are provided. The graphics processing unit includes: an execution unit, for performing shader execution and texture loading; a fixed-function unit, for executing a graphics rendering pipeline; a memory-access unit; a texture unit, for reading texture data from a memory via the memory-access unit according to the data requirement of the execution unit or the fixed-function unit; and a command stream parser, for receiving a draw command from a display driver, and transmitting the draw command to the execution unit or the fixed-function unit to perform graphics processing according to the type of draw command. When the command stream parser determines that the draw command is a specific draw command, the command stream parser transmits the draw command only to the fixed-function unit to perform graphics processing, and turns off power to the execution unit.


A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes an intermediate function f(x*) corresponding to the reduction value x*. The ALU computes a multiplication of the reduction value x* by the intermediate function f(x*) as the computation result of a trigonometric function.


A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).

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