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Zhang L.,Soochow University of China | Wu C.,Soochow University of China | Mao L.-F.,Soochow University of China | Zheng J.,Aicestar Technology Corporation
Micro and Nano Letters | Year: 2012

An integrated static random access memory (SRAM) compiler is proposed to reduce both leakage and dynamic power at circuit and architectural level. Based on source biasing scheme, an extra clamping diode in parallel with a pull-down n-type metal-oxide semiconductor transistor is inserted between the ground and source line of a SRAM cell to achieve reduction in the leakage current as well as data retention capability. Bit line charging/discharging current is greatly decreased by introducing extra Z decoding circuits and thus reducing dynamic power significantly. Test chips with 11 embedded SRAMs have been fabricated in UMC 55nm complementary metal-oxide semiconductor process and the measurement results have proved the effectiveness of the proposed technique. © 2012 The Institution of Engineering and Technology.

Zhang L.,Soochow University of China | Wu C.,Aicestar Technology Corporation | Wang Z.,Soochow University of China | Mao L.,Soochow University of China
Gaojishu Tongxin/Chinese High Technology Letters | Year: 2014

A new technique for design of a low power static random access memory (SRAM) was proposed to realize the simultaneous reduction of the leakage current and the dynamic power-consumption in the levels of circuit and architecture. The technique adopts a source biasing scheme (a NMOS transistor is inserted between the ground line and the SRAM cell) to reduce the leakage current. It requires an extra clamping diode in parallel with the NMOS transistor to avoid the floating virtual ground voltage and obtain the data retention capability. The SRAM is in an active mode when the NMOS transistor is turned on. Turning off the NMOS transistor can raise the source voltage and lead to a large reduction in the leakage current. Besides, the memory architecture is uniquely partitioned to decrease the number of half-selected SRAM cells and thus reducing the dynamic power. Power-gating techniques combined with high-Vth devices are applied to low power periphery circuits. Test chips with kinds of embedded SRAM instances were fabricated in the UMC 55 nm SP CMOS process and the measurement results proved the effectiveness and reliability of the proposed technique.

Wang Z.,Soochow University of China | Zhang Y.,Aicestar Technology Corporation | Zhang L.,Soochow University of China | Song X.,Portland State University
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates the failure ratio and keep the ratio less sensitive to signal slope. The novel amplifier structure is both simple and easy to control. A reliable design is given by considering both intrinsic and extrinsic offsets with reasonable speed and power consumption. A failure ratio analysis is performed. The result is validated using UMC 65nm process model. ©2010 IEEE.

Zhang Z.-Y.,Aicestar Technology Corporation | Zhang L.-J.,Soochow University of China | Zhang Y.-P.,Aicestar Technology Corporation | Huang R.-F.,Aicestar Technology Corporation | And 2 more authors.
Proceedings of International Conference on ASIC | Year: 2011

In this paper a two-port register file (RF) compiler with ultra high density design is presented. The memory implemented using a single port memory core, which is combined with a smart address selector circuit to reduce peripheral devices number and thus the silicon area is decreased significantly. The separate read and write replica scheme are implemented, with the improved write replica technique the memory compiler can accurately track the write timing over a wide range of memory array sizes and PVT variation. A test-chip with 13 embedded RF memories has been fabricated in UMC 55nm logic standard performance low-K process. The ultra high density design can markedly save 44.0% silicon area compared to conventional two-port RF (with 8T dual-port memory core) and only 4.3% area overhead compared to single-port RF (with 6T single-port memory core) for a 55nm 72Kb memory. © 2011 IEEE.

Huang R.,Aicestar Technology Corporation | Zheng J.,Aicestar Technology Corporation | Zhang L.,Soochow University of China | Zhang Z.,Aicestar Technology Corporation | And 2 more authors.
Proceedings of International Conference on ASIC | Year: 2011

This paper presents circuit techniques to improve read capability for single-end SA ROM design fabricated in UMC 55nm process. DV0 and DV1 margin are key features reflect read capability, and result show that DV0 enhanced significantly by using WL boosting schemes and DV1 enhanced by SA PMOS compensation (SAPC) structure. Combining WL boosting and SAPC technologies, the read fail problem in ROM could be solved easily which bring by leakages especially under 60nm process. © 2011 IEEE.

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