Time filter

Source Type

Ma Y.-Q.,Aicestar Technology Corporation | Zheng J.-B.,Aicestar Technology Corporation | Zhang Z.-Y.,Aicestar Technology Corporation | Yao Q.-S.,Aicestar Technology Corporation | And 2 more authors.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to doping fluctuation in the channel region. In this paper, a novel highly stable 10T SRAM cell is proposed which eliminates read SNM during read and write operation The cell suppresses active power owing to avoid the half select cell bit line fighting power. It also can work at ultra-low-voltage sub-threshold operation due to transistor stacking in the Read path to reduce leakage. ©2010 IEEE.


Zhang L.,Soochow University of China | Wu C.,Soochow University of China | Mao L.-F.,Soochow University of China | Zheng J.,Aicestar Technology Corporation
Micro and Nano Letters | Year: 2012

An integrated static random access memory (SRAM) compiler is proposed to reduce both leakage and dynamic power at circuit and architectural level. Based on source biasing scheme, an extra clamping diode in parallel with a pull-down n-type metal-oxide semiconductor transistor is inserted between the ground and source line of a SRAM cell to achieve reduction in the leakage current as well as data retention capability. Bit line charging/discharging current is greatly decreased by introducing extra Z decoding circuits and thus reducing dynamic power significantly. Test chips with 11 embedded SRAMs have been fabricated in UMC 55nm complementary metal-oxide semiconductor process and the measurement results have proved the effectiveness of the proposed technique. © 2012 The Institution of Engineering and Technology.


Huang R.,Aicestar Technology Corporation | Zheng J.,Aicestar Technology Corporation | Zhang L.,Soochow University of China | Zhang Z.,Aicestar Technology Corporation | And 2 more authors.
Proceedings of International Conference on ASIC | Year: 2011

This paper presents circuit techniques to improve read capability for single-end SA ROM design fabricated in UMC 55nm process. DV0 and DV1 margin are key features reflect read capability, and result show that DV0 enhanced significantly by using WL boosting schemes and DV1 enhanced by SA PMOS compensation (SAPC) structure. Combining WL boosting and SAPC technologies, the read fail problem in ROM could be solved easily which bring by leakages especially under 60nm process. © 2011 IEEE.


Zhang Z.-Y.,AiceStar Technology Corporation | Zhang L.-J.,Soochow University of China | Zhang Y.-P.,AiceStar Technology Corporation | Huang R.-F.,AiceStar Technology Corporation | And 2 more authors.
Proceedings of International Conference on ASIC | Year: 2011

In this paper a two-port register file (RF) compiler with ultra high density design is presented. The memory implemented using a single port memory core, which is combined with a smart address selector circuit to reduce peripheral devices number and thus the silicon area is decreased significantly. The separate read and write replica scheme are implemented, with the improved write replica technique the memory compiler can accurately track the write timing over a wide range of memory array sizes and PVT variation. A test-chip with 13 embedded RF memories has been fabricated in UMC 55nm logic standard performance low-K process. The ultra high density design can markedly save 44.0% silicon area compared to conventional two-port RF (with 8T dual-port memory core) and only 4.3% area overhead compared to single-port RF (with 6T single-port memory core) for a 55nm 72Kb memory. © 2011 IEEE.


Zhang L.,Soochow University of China | Wu C.,Aicestar Technology Corporation | Wang Z.,Soochow University of China | Mao L.,Soochow University of China
Gaojishu Tongxin/Chinese High Technology Letters | Year: 2014

A new technique for design of a low power static random access memory (SRAM) was proposed to realize the simultaneous reduction of the leakage current and the dynamic power-consumption in the levels of circuit and architecture. The technique adopts a source biasing scheme (a NMOS transistor is inserted between the ground line and the SRAM cell) to reduce the leakage current. It requires an extra clamping diode in parallel with the NMOS transistor to avoid the floating virtual ground voltage and obtain the data retention capability. The SRAM is in an active mode when the NMOS transistor is turned on. Turning off the NMOS transistor can raise the source voltage and lead to a large reduction in the leakage current. Besides, the memory architecture is uniquely partitioned to decrease the number of half-selected SRAM cells and thus reducing the dynamic power. Power-gating techniques combined with high-Vth devices are applied to low power periphery circuits. Test chips with kinds of embedded SRAM instances were fabricated in the UMC 55 nm SP CMOS process and the measurement results proved the effectiveness and reliability of the proposed technique.


Wang Z.,Soochow University of China | Zhang Y.,Aicestar Technology Co. | Zhang L.,Soochow University of China | Song X.,Portland State University
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates the failure ratio and keep the ratio less sensitive to signal slope. The novel amplifier structure is both simple and easy to control. A reliable design is given by considering both intrinsic and extrinsic offsets with reasonable speed and power consumption. A failure ratio analysis is performed. The result is validated using UMC 65nm process model. ©2010 IEEE.


Zhang L.-J.,Soochow University of China | Wu C.,Soochow University of China | Wu C.,Aicestar Technology Corporation | Ma Y.-Q.,Aicestar Technology Corporation | And 2 more authors.
IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) | Year: 2011

As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic VDD, negative wordline, and bitline floating schemes. All of them are achieved by controlling different terminal voltages of the SRAM cell in standby mode. On the other hand, performance loss occurs simultaneously with leakage saving. To validate the effectiveness of low power techniques, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 55 nm CMOS process with leakage current reduction techniques has been simulated. The results indicate that by using the dynamic VDD and source biasing schemes, greater leakage suppressing capability, although with a higher performance loss, can be obtained. Therefore, the SRAM cell optimization scheme must consider the trade-off between power consumption and speed performance.


Zhang L.,Soochow University of China | Yu Y.,AiceStar Technology Corporation | Zheng J.,AiceStar Technology Corporation | Song X.,Portland State University
International Journal of Electronics | Year: 2011

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55 nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3 GHz, and the test precision is about 35 ps at the typical process corner with supply voltage 1.0 V and temperature 25°C. © 2011 Taylor & Francis.


Wu C.,Soochow University of China | Zhang L.,Soochow University of China | Lu Z.,Soochow University of China | Ma Y.,Aicestar Technology Corporation | Zheng J.,Aicestar Technology Corporation
2010 International SoC Design Conference, ISOCC 2010 | Year: 2010

Reducing standby supply voltage to DRV can sharply decrease leakage power. In this paper, a feedback monitor scheme for standby VDD scaling is proposed. The feedback scheme utilizes the same memory cell to obtain exactly the same performance with SRAM core cells and thus to monitor approximate DRV tail of SRAM array. Based on Monte-Carlo DRV distribution along with its dependencies on body-bias and source-bias voltage, we add controlling options to regulate the DRV of monitor cells and then to approach the worst-case DRV of core cells. The feedback monitor scheme for detecting DRV is implemented with bank-based SRAM design. Simulation results on 55nm CMOS process indicates that for a 512KB SRAM, leakage power savings are achieved in different process corners compared to conventional SRAM structure. ©2010 IEEE.


Wu C.,Soochow University of China | Wu C.,Aicestar Technology Corporation | Zhang L.-J.,Soochow University of China | Wang Y.,Aicestar Technology Corporation | Zheng J.-B.,Aicestar Technology Corporation
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

In this paper, an integrated 512KB SRAM architecture with low power circuit design is presented. An extra Z decoding circuit is introduced, which is combined with divided wordline/bitline scheme to reduce half-selected memory cells and thus dynamic power is decreased significantly. In circuit level, we utilize source biasing scheme to achieve leakage reduction and adopt an extra clamping diode in parallel with pull-down NMOS transistor to obtain data retention capability. Besides, power-gating method is proposed for wordline driver circuits. Simulation results on 55nm CMOS process indicates that leakage power and dynamic power can be saved by 66.7% and 27.9% respectively compared to conventional SRAM structure with performance penalty less than 3%. ©2010 IEEE.

Loading Aicestar Technology Corporation collaborators
Loading Aicestar Technology Corporation collaborators