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Patent
Advanced Semiconductor Engineering Inc. | Date: 2015-08-25

The present disclosure relates to an optical module, including: a carrier, a emitter, a detector and an encapsulant. The carrier has a first surface. The emitter is disposed above the first surface. The detector is disposed above the first surface. The encapsulant is disposed on the first surface and exposes at least a portion of the emitter.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-01-07

An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2015-07-09

The present disclosure relates to an optical module. In an embodiment, the optical module includes a carrier, a light source, a light detector, and a first polarizer. The light source and the light detector are disposed adjacent to a first surface of the carrier. The first polarizer is disposed on the light detector. The optical module is configured to polarize light emitted from the light source into a first polarization direction substantially perpendicular to a second polarization direction of light permitted through the first polarizer.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2015-05-05

A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2015-12-16

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

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