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Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-09-15

An optical device includes an active optical component including an optical area, an encapsulant covering the active optical component, and a passive optical component adhered to the encapsulant above the active optical component. The passive optical component has an optical axis, and the optical axis is substantially aligned with a center of the optical area.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-10-19

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-11-29

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2017-01-19

The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2017-01-13

A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2015-10-15

A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad. The interconnection element connects the second bottom pad and the first top pad. The interconnection element includes a first cupped portion and a second arcuate portion, where the first portion is connected to the first top pad and the second portion is connected to the second bottom pad. The first portion and the second portion together define the interconnection element as a monolithic component. The encapsulant is disposed between the first semiconductor substrate and the second semiconductor substrate, and covers the semiconductor die and the interconnection element.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-10-14

The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2017-01-18

The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-08-29

A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.


Patent
Advanced Semiconductor Engineering Inc. | Date: 2016-08-17

A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

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