AdMOS GmbH Advanced Modeling Solutions

Frickenhausen, Germany

AdMOS GmbH Advanced Modeling Solutions

Frickenhausen, Germany
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Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: GC-ICT-2011.6.8 | Award Amount: 5.75M | Year: 2012

Smart Power ICs are extensively used in automotive embedded systems due to their unique capabilities to merge low power and high voltage devices on the same chip, at competitive cost. In such devices, induced electrical coupling noise due to switching of the power stages, when integrating such high voltage (HV) devices with low voltage (LV) functions, is a big issue. During switching, parasitic voltages and currents, consisting of electrons and holes, lead to a local shift of the substrate potential that can reach hundreds of millivolts. This electrical coupling noise can severely disturb low voltage circuits. Such parasitic signals are known to represent the major cause of failure and costly circuit redesign in power integrated circuits. Furthermore, parasitic carrier injections are considerably increased under high temperature operation such as those encountered in automotive applications where this problem is even more severe since these dedicated ICs need to be highly reliable and stable with time. Most solutions are layout dependent and are thus difficult to optimize using available electrical simulator software. The lack for a model strategy that would enable to simulate accurately the injection of minority carriers in the substrate as part of the HV model, as well as its propagation in the substrate, is one of the main reasons for this critical situation. This lack for a design methodology prohibits an efficient design strategy and fails at giving clear predictions of perturbations in high voltage integrated circuits. This picture motivates this project proposal where all these aspects are addressed to create a link between circuit design, modeling and implementation in innovative computer aided design tools. This concerns smart power ICs dedicated to automotive applications requiring co-integration of high voltage power stages with low voltage analog/digital blocks on the same chip, still being reliable\nwhen operating at high temperature.


Grant
Agency: European Commission | Branch: H2020 | Program: MSCA-RISE | Phase: MSCA-RISE-2014 | Award Amount: 742.50K | Year: 2014

Our project aims to fill the gap between flexible electronic technology and design by developing highly predictive, generic, open-source, design-oriented organic and oxide based TFT compact model libraries, to be integrated in commercial Electron Design Automation (EDA) environments for full large area low cost circuit design for novel applications. These model libraries will be released together with parameter extraction standard templates to assist in the fast transfer between initial prototype device measurements to full product design. Such a facility will open the opportunity for wide flexible electronics design


Grant
Agency: European Commission | Branch: FP7 | Program: MC-IAPP | Phase: PEOPLE-2007-3-1-IAPP | Award Amount: 1.92M | Year: 2008

The goal of our Network is to address the full development chain of Compact Modeling (CM) of advanced CMOS and III-V technologies, from the technology level to the system level. Our mission is driven by the need to enhance scientific knowledge, transfer scientific and technological knowledge from academia to industry, to strengthen the European integrated circuit (IC) industry with powerful design automation methodologies and to achieve integration of European research in a fragmented area for the benefit of both young and experienced researchers.


Darbandy G.,Rovira i Virgili University | Darbandy G.,AdMOS GmbH Advanced Modeling Solutions | Gneiting T.,AdMOS GmbH Advanced Modeling Solutions | Alius H.,AdMOS GmbH Advanced Modeling Solutions | And 3 more authors.
Semiconductor Science and Technology | Year: 2013

In this paper, automatic parameter extraction techniques of Agilent's IC-CAP modeling package are presented to extract our explicit compact model parameters. This model is developed based on a surface potential model and coded in Verilog-A. The model has been adapted to Trigate MOSFETs, includes short channel effects (SCEs) and allows accurate simulations of the device characteristics. The parameter extraction routines provide an effective way to extract the model parameters. The techniques minimize the discrepancy and error between the simulation results and the available experimental data for more accurate parameter values and reliable circuit simulation. Behavior of the second derivative of the drain current is also verified and proves to be accurate and continuous through the different operating regimes. The results show good agreement with measured transistor characteristics under different conditions and through all operating regimes. © 2013 IOP Publishing Ltd.


Darbandy G.,Rovira i Virgili University | Darbandy G.,AdMOS GmbH Advanced Modeling Solutions | Gneiting T.,AdMOS GmbH Advanced Modeling Solutions | Alius H.,AdMOS GmbH Advanced Modeling Solutions | And 3 more authors.
Solid-State Electronics | Year: 2013

Direct Tunneling (DT) and Trap Assisted Tunneling (TAT) gate leakage current parameters have been extracted and verified considering automatic parameter extraction approach. The industry standard package IC-CAP is used to extract our leakage current model parameters. The model is coded in Verilog-A and the comparison between the model and measured data allows to obtain the model parameter values and parameters correlations/relations. The model and parameter extraction techniques have been used to study the impact of parameters in the gate leakage current based on the extracted parameter values. It is shown that the gate leakage current depends on the interfacial barrier height more strongly than the barrier height of the dielectric layer. There is almost the same scenario with respect to the carrier effective masses into the interfacial layer and the dielectric layer. The comparison between the simulated results and available measured gate leakage current transistor characteristics of Trigate MOSFETs shows good agreement. © 2013 Elsevier Ltd. All rights reserved.


Zou H.,CNRS Laboratory for Informatics | Moursy Y.,CNRS Laboratory for Informatics | Iskander R.,CNRS Laboratory for Informatics | Chaput J.-P.,CNRS Laboratory for Informatics | And 9 more authors.
Proceedings of the 2015 IEEE 20th International Mixed-Signals Test Workshop, IMSTW 2015 | Year: 2015

Smart Power IC integrating high voltage devices with low voltage control blocks becomes more and more popular in automotive industry recently. Minority carriers injected into the substrate during switching of high power stages cause malfunction of sensitive nearby low voltage devices. Sometimes this may be destructive due to the presence of triggered latch up. The minority carriers propagation is extremely hard to model and difficult to predict using existing commercial standard design flow. In this paper, we propose a Computer-Aided-Design solution to characterise the substrate vertical and lateral parasitic for Smart Power IC in automotive applications. Investigation of complex benchmark structures is presented. SPICE simulations are performed for extracted 3D substrate netlist and compared to measurements. Good fitting between simulation and measurement validates the effectiveness and accuracy of the proposed CAD tool. © 2015 IEEE.

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