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Darbandy G.,Rovira i Virgili University | Darbandy G.,AdMOS GmbH Advanced Modeling Solutions | Gneiting T.,AdMOS GmbH Advanced Modeling Solutions | Alius H.,AdMOS GmbH Advanced Modeling Solutions | And 3 more authors.
Solid-State Electronics | Year: 2013

Direct Tunneling (DT) and Trap Assisted Tunneling (TAT) gate leakage current parameters have been extracted and verified considering automatic parameter extraction approach. The industry standard package IC-CAP is used to extract our leakage current model parameters. The model is coded in Verilog-A and the comparison between the model and measured data allows to obtain the model parameter values and parameters correlations/relations. The model and parameter extraction techniques have been used to study the impact of parameters in the gate leakage current based on the extracted parameter values. It is shown that the gate leakage current depends on the interfacial barrier height more strongly than the barrier height of the dielectric layer. There is almost the same scenario with respect to the carrier effective masses into the interfacial layer and the dielectric layer. The comparison between the simulated results and available measured gate leakage current transistor characteristics of Trigate MOSFETs shows good agreement. © 2013 Elsevier Ltd. All rights reserved. Source


Darbandy G.,Rovira i Virgili University | Darbandy G.,AdMOS GmbH Advanced Modeling Solutions | Gneiting T.,AdMOS GmbH Advanced Modeling Solutions | Alius H.,AdMOS GmbH Advanced Modeling Solutions | And 3 more authors.
Semiconductor Science and Technology | Year: 2013

In this paper, automatic parameter extraction techniques of Agilent's IC-CAP modeling package are presented to extract our explicit compact model parameters. This model is developed based on a surface potential model and coded in Verilog-A. The model has been adapted to Trigate MOSFETs, includes short channel effects (SCEs) and allows accurate simulations of the device characteristics. The parameter extraction routines provide an effective way to extract the model parameters. The techniques minimize the discrepancy and error between the simulation results and the available experimental data for more accurate parameter values and reliable circuit simulation. Behavior of the second derivative of the drain current is also verified and proves to be accurate and continuous through the different operating regimes. The results show good agreement with measured transistor characteristics under different conditions and through all operating regimes. © 2013 IOP Publishing Ltd. Source


Zou H.,CNRS Laboratory for Informatics | Moursy Y.,CNRS Laboratory for Informatics | Iskander R.,CNRS Laboratory for Informatics | Chaput J.-P.,CNRS Laboratory for Informatics | And 9 more authors.
Proceedings of the 2015 IEEE 20th International Mixed-Signals Test Workshop, IMSTW 2015 | Year: 2015

Smart Power IC integrating high voltage devices with low voltage control blocks becomes more and more popular in automotive industry recently. Minority carriers injected into the substrate during switching of high power stages cause malfunction of sensitive nearby low voltage devices. Sometimes this may be destructive due to the presence of triggered latch up. The minority carriers propagation is extremely hard to model and difficult to predict using existing commercial standard design flow. In this paper, we propose a Computer-Aided-Design solution to characterise the substrate vertical and lateral parasitic for Smart Power IC in automotive applications. Investigation of complex benchmark structures is presented. SPICE simulations are performed for extracted 3D substrate netlist and compared to measurements. Good fitting between simulation and measurement validates the effectiveness and accuracy of the proposed CAD tool. © 2015 IEEE. Source

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