News Article | May 1, 2017
The Chan Zuckerberg Biohub (CZ Biohub) today announced Gajus Worthington has joined its management team as chief operating officer, bringing his more than 17 years of executive management experience in the life science sector to the non-profit, medical research organization. “CZ Biohub is poised to catalyze major biological discoveries at an unprecedented pace and contribute fundamentally in humanity's fight against disease,” said Worthington. “I am honored to be part of the amazing team Joe and Steve are assembling, and I’m eager to build out an operation that will help realize CZ Biohub’s incredible potential. This is a very exciting opportunity and I cannot wait to dig in.” “Gajus brings a unique combination of technical and managerial experience that will help us evolve from our startup phase into a leading non-profit research institution,” said Joseph DeRisi, co-president of CZ Biohub. “He managed Fluidigm as the company grew from its founding to many prosperous years as a publicly traded company. We are fortunate to have someone with that experience join our leadership team.” Worthington was a co-founder of Fluidigm Corporation and served as President and CEO from 1999 to 2016. Prior to Fluidigm, he held a variety of engineering, marketing and management positions at Actel Corporation. He earned a Bachelor’s degree in physics and a Master’s degree in electrical engineering from Stanford University. He is an elected fellow of the American Institute for Medical and Biological Engineering (AIMBE). “I have known Gajus for many years and I couldn’t be more excited about having him in the role of COO,” said Stephen Quake, co-president of CZ Biohub. “It is rare to find someone with his intellect, passion for science and technology, and track record of building a successful organization. I worked with Gajus at Fluidigm and I look forward to working with him again as he helps us scale CZ Biohub.” The CZ Biohub is an independent, non-profit, medical research organization collaborating with the University of California, Berkeley, Stanford University and the University of California, San Francisco to harness the power of science, technology and human capacity to cure, prevent or manage all diseases during our children’s lifetime. For more information about the CZ Biohub, visit https://czbiohub.org.
News Article | May 4, 2017
The full presentation, along with other important documents related to these matters, can be found at www.CypressFirst.com or on the website of the Securities and Exchange Commission (www.sec.gov). WHETHER OR NOT YOU PLAN TO ATTEND THE ANNUAL MEETING, YOUR PROMPT ACTION IS IMPORTANT. MAKE YOUR VIEWS CLEAR TO THE BOARD BY AUTHORIZING A PROXY TO VOTE FOR EACH PROPOSAL BY FOLLOWING THE INSTRUCTIONS ON THE PROXY CARD. YOUR VOTE IS IMPORTANT, NO MATTER HOW MANY OR HOW FEW SHARES OF COMMON STOCK YOU OWN. Do not return any white proxy card that you may receive from the Company relating to the Annual Meeting, even as a protest vote. If you have already submitted a white proxy card to the Company relating to the Annual Meeting, it is not too late to change your vote. To revoke your prior proxy and change your vote, simply sign, date and return the proxy card in the postage-paid envelope provided. Only your latest signed and dated proxy will be counted. For more information about the CypressFirst nominees, please read the Proxy Statement. The Proxy Statement, as well as other related materials, can be viewed online at www.CypressFirst.com. For additional information or assistance, please contact MacKenzie Partners, Inc., the firm assisting CypressFirst in the solicitation of proxies: Additional Information and Where to Find It T.J. Rodgers is the founding CEO of Cypress Semiconductor Corporation (the "Company"). Rodgers, J. Daniel McCranie and Camillo Martino may be deemed to be participants in the solicitation of proxies from stockholders in connection with the 2017 Annual Meeting of Stockholders (the "Annual Meeting") of the Company. Rodgers, McCranie and Martino have filed a definitive proxy statement (the "CypressFirst Proxy Statement") and accompanying proxy card with the Securities and Exchange Commission (the "SEC") in connection with his solicitation of proxies for the Annual Meeting. Rodgers owns or controls voting of 8,727,619 shares of the Company's common stock. McCranie and Martino own 25,000 and 10,000 shares, respectively, of the Company's common stock. Additional information regarding such participants, including their direct or indirect interests, by security holdings or otherwise, are included in the CypressFirst Proxy Statement and may be included in other relevant documents to be filed with the SEC in connection with the Annual Meeting. Rodgers, McCranie and Martino have mailed the definitive CypressFirst Proxy Statement and a proxy card pursuant to applicable SEC rules. STOCKHOLDERS ARE URGED TO READ THE CYPRESSFIRST PROXY STATEMENT (INCLUDING ANY AMENDMENTS OR SUPPLEMENTS THERETO) AND ANY OTHER RELEVANT DOCUMENTS THAT RODGERS, McCRANIE AND MARTINO HAVE FILED OR WILL FILE WITH THE SEC WHEN THEY BECOME AVAILABLE BECAUSE THEY WILL CONTAIN IMPORTANT INFORMATION. Stockholders may obtain, free of charge, copies of the definitive CypressFirst Proxy Statement and any other related documents filed by CypressFirst with respect to the Company with the SEC in connection with the Annual Meeting at the SEC's website ( ). In addition, copies of such materials, when available, may be requested free of charge from MacKenzie Partners, Inc., 105 Madison Avenue, New York, NY 10016 or toll-free at (800) 322-2885 or by email: . About J. Daniel McCranie J. Daniel McCranie has served as Chairman at ON Semiconductor Corp. since 2002 and is scheduled to resign from the board in May 2017. He previously served as Non-Executive Chairman at Freescale Semiconductor, Inc. He served on the Board of Directors at Mentor Graphics Corp. from 2012 until its sale to Siemens Corporation in April 2017. He served on the Board of Directors of Cypress Semiconductor Corp. from 2005 through 2014. He has served as Chairman of Actel Corporation, Chairman of Virage Logic, Inc, Chairman of Xicor Corporation, and Board Director of California Microdevices, Inc. McCranie was previously employed as Executive Vice President- Sales & Applications by Cypress Semiconductor Corp., President & Chief Executive Officer by Virage Logic Corp., Vice President-Sales & Marketing by Cypress Semiconductor Corp., and Chairman, President & Chief Executive Officer by SEEQ Technology, Inc. About Camillo Martino Camillo Martino has served as a member of the Board of Directors of MagnaChip Semiconductor Corp. since August 2016. He was appointed to the Board of Directors of MosChip in April 2017. Martino has served as a member of the Board of Directors of VVDN Technologies, a private company, since March 2016 and as Vice Chairman of the Board of Directors of SAI Technology, Inc., a private company, since April 2015. Previously, he served as director and CEO of Silicon Image, Inc.; COO at SAI Technology Inc.; and President, CEO and Director of Cornice Inc. He also served as Executive Vice President and COO of chipmaker Zoran Corporation. His career began at National Semiconductor Corporation, where he held multiple positions over a nearly 14-year tenure at the Company. About T.J. Rodgers T.J. Rodgers co-founded Cypress Semiconductor Corporation in 1982 and served as the Company's President and Chief Executive Officer until April 2016 and as a member of its Board of Directors until August 2016. He is a former chairman of the Semiconductor Industry Association (SIA) and SunPower Corp. and currently sits on the boards of directors of high-technology companies, including Bloom Energy (fuel cells), Enphase (solar energy electronics), WaterBit (precision agriculture) and Enovix (silicon lithium-ion batteries). He has been honored for his foundational support over a 20-year period of the Second Harvest Food Bank of Santa Clara and San Mateo Counties and the California Association of African American Educators. Rodgers received his bachelor's degree from Dartmouth College, graduating as salutatorian with majors in chemistry and physics. He received his master's degree and Ph.D. in electrical engineering from Stanford University. While pursuing his Ph.D. degree, Rodgers invented the VMOS process technology, which he later licensed to American Microsystems, Inc. To view the original version on PR Newswire, visit:http://www.prnewswire.com/news-releases/cypressfirst-releases-new-investor-presentation-300451319.html
Chen D.,University of Illinois at Urbana - Champaign |
Cong J.,University of California at Los Angeles |
Dong C.,University of Illinois at Urbana - Champaign |
He L.,University of California at Los Angeles |
And 2 more authors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2010
This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap. We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap , DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process. © 2006 IEEE.
Microsemi and Actel Corporation | Date: 2010-08-10
Kennings A.,University of Waterloo |
Mishchenko A.,University of California at Berkeley |
Vorwerk K.,Actel Corporation |
Pevzner V.,Actel Corporation |
Kundu A.,Actel Corporation
Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010 | Year: 2010
The ability to efficiently match logic functions to structures of K-input look-up tables (K-LUTs) is a central problem in FPGA resynthesis algorithms. This paper addresses the problem of matching logic functions of ∼ 9 to 12 inputs to K-LUT structures. Our method is based on the off-line generation of libraries of LUT structures. During resynthesis, matching is accomplished efficiently using NPN encoding and hash table look-ups. Generating an effective library of LUT structures may seem prohibitive due to the overwhelming number of logic functions which must be considered and represented in the library. We show that, by careful consideration of which logic functions and LUT structures to keep, it is possible to generate useful, compact libraries. We present numerical results demonstrating the effectiveness of our ideas when used during area-oriented resynthesis after FPGA technology mapping. © 2010 IEEE.
El-Abd M.,University of Waterloo |
Hassan H.,Actel Corporation |
Anis M.,University of Waterloo |
Kamel M.S.,University of Waterloo |
Elmasry M.,University of Waterloo
Applied Soft Computing Journal | Year: 2010
Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR. © 2009 Elsevier B.V. All rights reserved.
Rezgui S.,Actel Corporation |
Louris P.,Actel Corporation |
Sharmin R.,University of Toronto
IEEE Transactions on Nuclear Science | Year: 2010
A comprehensive SEE characterization at high-frequencies (up to 120 MHz) of the new space-flight RTAX-D antifuse-based FPGA family is presented. SEE hardening-by-design techniques in the main FPGA programmable architectures have been implemented. It is evaluated in-beam to show their efficacy in mitigating SETs with little area and time penalty. In particular, SEU/SET mitigation solutions were implemented in the new embedded DSP blocks and the FPGA core and tested in heavy-ion beams. Comparing to its predecessor, RTAX-S, these mitigations reduce the overall orbital error-rates by an order of magnitude. © 2010 IEEE.
Kennings A.,Actel Corporation |
Vorwerk K.,Actel Corporation |
Kundu A.,Actel Corporation |
Pevzner V.,Actel Corporation |
Fox A.,Actel Corporation
ACM Transactions on Reconfigurable Technology and Systems | Year: 2011
Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables; specifically, the logic block is a partial LUT, but it possesses more inputs than a typical LUT. An analysis of the logic block is presented, and techniques for postmapping area recovery and timing-driven buffer insertion are also described. Numerical results are put forth which substantiate the efficacy of the proposed methods using real circuits mapped to a commercial FPGA architecture. © 2011 ACM.
Rezgui S.,Actel Corporation |
McCollum J.,Actel Corporation |
Won R.,Actel Corporation
IEEE Transactions on Nuclear Science | Year: 2010
SET propagations in ASIC-like and FPGA-like digital circuits are investigated, using 90-nm test structures, by fault injection and radiation tests. SET fault injection tests are used to show the dependence of the final SET-pulse on the design and layout of the logic circuit. © 2010 IEEE.
Actel Corporation | Date: 2011-06-10
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.