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Chen D.,University of Illinois at Urbana - Champaign | Cong J.,University of California at Los Angeles | Dong C.,University of Illinois at Urbana - Champaign | He L.,University of California at Los Angeles | And 2 more authors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2010

This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap. We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap , DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process. © 2006 IEEE.


Rezgui S.,Actel Corporation | Won R.,Actel Corporation | Tien J.,Microsemi | George J.,The Aerospace Corporation | And 2 more authors.
Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS | Year: 2011

SET propagation and mitigation in 65-nm test structures are investigated. Radiation tests show a clear distortion of the SET pulse-widths related to the structures' design and layout and the efficacy of the employed mitigation techniques. © 2011 IEEE.


Trademark
Microsemi and Actel Corporation | Date: 2010-08-10

Integrated circuits; computer hardware for programming and debugging integrated circuits.


Kennings A.,University of Waterloo | Mishchenko A.,University of California at Berkeley | Vorwerk K.,Actel Corporation | Pevzner V.,Actel Corporation | Kundu A.,Actel Corporation
Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010 | Year: 2010

The ability to efficiently match logic functions to structures of K-input look-up tables (K-LUTs) is a central problem in FPGA resynthesis algorithms. This paper addresses the problem of matching logic functions of ∼ 9 to 12 inputs to K-LUT structures. Our method is based on the off-line generation of libraries of LUT structures. During resynthesis, matching is accomplished efficiently using NPN encoding and hash table look-ups. Generating an effective library of LUT structures may seem prohibitive due to the overwhelming number of logic functions which must be considered and represented in the library. We show that, by careful consideration of which logic functions and LUT structures to keep, it is possible to generate useful, compact libraries. We present numerical results demonstrating the effectiveness of our ideas when used during area-oriented resynthesis after FPGA technology mapping. © 2010 IEEE.


El-Abd M.,University of Waterloo | Hassan H.,Actel Corporation | Anis M.,University of Waterloo | Kamel M.S.,University of Waterloo | Elmasry M.,University of Waterloo
Applied Soft Computing Journal | Year: 2010

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR. © 2009 Elsevier B.V. All rights reserved.


Rezgui S.,Actel Corporation | Louris P.,Actel Corporation | Sharmin R.,University of Toronto
IEEE Transactions on Nuclear Science | Year: 2010

A comprehensive SEE characterization at high-frequencies (up to 120 MHz) of the new space-flight RTAX-D antifuse-based FPGA family is presented. SEE hardening-by-design techniques in the main FPGA programmable architectures have been implemented. It is evaluated in-beam to show their efficacy in mitigating SETs with little area and time penalty. In particular, SEU/SET mitigation solutions were implemented in the new embedded DSP blocks and the FPGA core and tested in heavy-ion beams. Comparing to its predecessor, RTAX-S, these mitigations reduce the overall orbital error-rates by an order of magnitude. © 2010 IEEE.


Kennings A.,Actel Corporation | Vorwerk K.,Actel Corporation | Kundu A.,Actel Corporation | Pevzner V.,Actel Corporation | Fox A.,Actel Corporation
ACM Transactions on Reconfigurable Technology and Systems | Year: 2011

Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables; specifically, the logic block is a partial LUT, but it possesses more inputs than a typical LUT. An analysis of the logic block is presented, and techniques for postmapping area recovery and timing-driven buffer insertion are also described. Numerical results are put forth which substantiate the efficacy of the proposed methods using real circuits mapped to a commercial FPGA architecture. © 2011 ACM.


Rezgui S.,Actel Corporation | McCollum J.,Actel Corporation | Won R.,Actel Corporation
IEEE Transactions on Nuclear Science | Year: 2010

SET propagations in ASIC-like and FPGA-like digital circuits are investigated, using 90-nm test structures, by fault injection and radiation tests. SET fault injection tests are used to show the dependence of the final SET-pulse on the design and layout of the logic circuit. © 2010 IEEE.


Vorwerk K.,Actel Corporation | Kennings A.,Actel Corporation | Pevzner V.,Actel Corporation | Kundu A.,Actel Corporation | And 3 more authors.
IET Computers and Digital Techniques | Year: 2010

This study discusses the implementation of two sets of techniques for minimising power within the context of a commercial field programmable gate array () placement flow. The first aspect discussed in this work is a power-aware objective function for placement. In particular, a capacitance model for global nets is described which allows the net power in a design to be dramatically reduced. The second aspect describes augmentations to a physical re-synthesis flow, which help to reduce area and power by optimising the number of combinational and sequential cells. The results are quantified across a suite of 119 industrial benchmarks targeting the Actel IGLOO architecture. Power measurements show that the techniques described in this study reduce dynamic power by 13% on average, with a 6.7% average improvement in timing performance across the suite. © 2010 © The Institution of Engineering and Technology.


Patent
Actel Corporation | Date: 2011-06-10

An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

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