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Chen D.,University of Illinois at Urbana - Champaign | Cong J.,University of California at Los Angeles | Dong C.,University of Illinois at Urbana - Champaign | He L.,University of California at Los Angeles | And 2 more authors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2010

This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap. We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap , DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process. © 2006 IEEE. Source


El-Abd M.,University of Waterloo | Hassan H.,Actel Corporation | Anis M.,University of Waterloo | Kamel M.S.,University of Waterloo | Elmasry M.,University of Waterloo
Applied Soft Computing Journal | Year: 2010

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR. © 2009 Elsevier B.V. All rights reserved. Source


Trademark
Microsemi and Actel Corporation | Date: 2009-11-17

Integrated circuits; integrated circuit intellectual property cores; computer software for operating, programming and debugging integrated circuits; computer software for designing, synthesizing, simulating, placing and routing circuits implemented in a field programmable gate array device; computer hardware for programming and debugging integrated circuits.


Trademark
Microsemi and Actel Corporation | Date: 2010-08-10

Integrated circuits; computer hardware for programming and debugging integrated circuits.


Trademark
Microsemi and Actel Corporation | Date: 2008-02-12

Integrated circuits.

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