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Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2011.3.4 | Award Amount: 3.65M | Year: 2011

Safety-critical systems are important parts of our daily life. Those systems are also called dependable systems, as our lives can depend on them. Examples are controllers in an airplane, breaking controller in a car, or a train control system. Those safety-critical systems need to be certified and the maximum execution time needs to be bounded and known so that response times can be assured when critical actions are needed. Even with high performance processors in our desktop PCs we notice once in a while that the PC is frozen for a few seconds. For a safety-critical system such a pause can result in a catastrophic failure.\nThe mission of T-CREST is to develop tools and build a system that prevents pauses by identifying and addressing the causes for possible pauses. The T-CREST time-predictable system will simplify the safety argument with respect to maximum execution time striving to double performance for 4 cores and to be 4 times faster for 16 cores than a standard processor in the same technology (e.g., FPGA). Thus the T-CREST system will result in lower costs for safety relevant applications reducing system complexity and at the same time faster time-predictable execution.\nStandard computer architecture is driven by the following paradigm: make the common case fast and the uncommon case correct. This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modelling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative.\nWe need a sea change and we shall take the constructive approach by designing computer architectures where predictable timing is a first-order design factor. For real-time systems we propose to design architectures with a new paradigm: make the worst-case fast and the whole system easy to analyse. Despite the advantages of analysable system resources, only a few research projects exist in the field of hardware optimized for the WCET.\nWithin the project we will propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc.) will be a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) will provide a solution for the need of more processing power in the real-time domain.\nNext to the hardware (processor, interconnect, memories), a compiler infrastructure will be developed in the project. WCET aware optimization methods will be developed along with detailed timing models such that the compiler benefits from the known behaviour of the hardware. The WCET analysis tool aiT will be adapted to support the developed hardware and guide the compilation.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.3 | Award Amount: 3.93M | Year: 2008

The project proposal is concerned with embedded systems that are characterized by efficiency requirements such as average-case performance, resource utilization, and power consumption on the one hand and worst-case constraints on the other. This combination of requirements typically occurs in application domains such as automotive, aeronautics, multi-media and industrial automation. Embedded systems with critical constraints need offline guarantees for the satisfaction of these constraints. Unfortunately, it can be observed that in computer system design the gap between average case and worst-case behaviour increases rapidly. This entails a decreasing precision of performance-analysis results, even for combination of the strongest analyses available. Therefore, a new research and design discipline is proposed that looks at predictability and efficiency in a synergistic manner and that involves all levels of abstraction and implementation in embedded-system design. This paradigm shift overcomes the tendency to either optimize efficiency only or predictability only in favour of an approach that takes into account the multi-objective nature of the problem.
The proposed approach consists of a combination of several methods, i.e.
(a)\tdesign-space exploration on the hardware architecture level to identify good designs offering combinations of strong performance with good predictability,
(b)\ta synergistic development of models, design methods and matching analysis tools that extract precise system-behaviour properties, and
(c)\ta transformation of the established separation-of-concerns abstraction principle into a new principle, resource-aware abstraction.
Partners from the automotive and aeronautics domains pose design challenges based on experience in the design of time-critical embedded systems. These challenges will be taken up by the academic partners. Prototype architectures, design methods and analysis tools will be developed to solve the challenges


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.3 | Award Amount: 2.09M | Year: 2007

A large class of embedded systems has safety, availability, reliability, timing and performance requirements. Timing analysis is needed in many steps of the development process; it is a key to rapid designing and prototyping of embedded systems, to reduce system overall cost through efficient resource management (especially: tradeoffs when co-developing hardware and software), to find bottlenecks in the software, and to validate that the system meets its timing requirements. There is a growing awareness of the importance of correct timing for these systems, however, there is still a lack of efficient methods and tools for timing assessment and validation that can be used in European industry. The existing timing analysis technology by far does not exploit the potential inherent in European research results and timing tools. The ALL-TIMES project aims at combining and developing research results and timing tools currently available and thus to strengthen the European lead in the timing analysis area. The ALL-TIMES project will enable interoperability of tools from SMEs and universities, and develop integrated tool chains using open tool frameworks and interfaces. By combining research results and commercial tools, ALL-TIMES will ensure the flow of ideas from basic research to practice. ALL-TIMES will strengthen the competitiveness of several key industries in Europe, not only the automotive and aerospace areas (where partial awareness already exists) but also automation, manufacturing, robotics, medical, communication, and multimedia, and other market areas where timing is of importance.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.3 | Award Amount: 7.38M | Year: 2008

The INTERESTED project has been built to exactly match the goals defined within the Objective ICT-2007-3.3b Suites of Interoperable design tools for rapid design and prototyping, namely creating a reference open interoperable embedded systems tool-chain, fulfilling the needs of the industry for designing and prototyping embedded systems
This project regroups a consortium of leading edge European Embedded Systems Tools Vendors, all being high tech innovatives SMEs, as well as European Major Tool Users representing several industries that are both integrating massively embedded systems and contributing to the overall competitiveness of Europe: Aerospace, Automotive, Railway and Transportation and Energy.
The method followed in the project is the following:
- Major Tool Users will bring their requirements for the Tool-Chain content, structuring, features, interoperability architecture and characteristics;
- Cover the full scope of Embedded Systems and SW engineering disciplines, spanning:
. System and Application Software Design Modelling, Verification and Code Generation
. Networking and RTOS execution platforms, Hardware-Dependent Software verification and Code Generation
. Timing Analysis and code execution verification
- Validate the use and openness of the INTERESTED tool-chain on Industrial Validators representing key application domains for European leading industries;
- Demonstrate openness and interoperability within the INTERESTED Tool-Chain of Commercial Off-The-Shelf (COTS) and Open Source tools to the benefit of the users and tool suppliers communities.
In summary, INTERESTED aims at realize the first European-Wide tool reference development environment ever, validated by Major Tool Users through real-life Industrial Validators, ensuring an integrated, lower cost, highly dependable, safe and efficient development process to the benefit of critical EU industries.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2011.3.3 | Award Amount: 4.01M | Year: 2011

Pushed by economical and ecological stakes, embedded systems from the avionics, automotive and automation domains, featuring real-time, safety and critical capabilities have to face increasing performance needs that will no more be satisfied by existing architectures based on single-cores. Current trends are to take benefit from multi-core processors high performance in replacing single-cores by multi-cores which raises predictability and isolation challenges for timing and mixed criticality aspects. This is mainly due to the inadequateness and inability of current approaches to effectively handle reliability and the cause of non-deterministic behaviour on multi-cores.\nFacing multi-core architectures inevitable use, CERTAINTY will introduce a disruptive methodology for the design of complex critical applications allowing safety and time criticality aspects composition, taking into account unpredictability of shared resource availability as elements of the problem space, identify analysis methods and techniques supporting this new approach and demonstrate the applicability of these techniques through meaningful examples of complex control functions.\nNew methodology and design tools, applicable in diverse industrial sectors, will be validated in an avionics application on a multi-core architecture: an existing Flight Management System will be analyzed using the CERTAINTY Methodology and Analysis Tools to specify which part could be at which critical level redesigned and composed according to the methodology. The system design will be evaluated to show that relevant safety requirements are met (i.e. ability to ensure partitioning/isolation, ability to provide a WCET, system determinism and incrementality), contributing to the certification process on new architecture generations. The major result will be a Proof of Concept of a design methodology, resultant Analysis Methodologies and associated synthesis tools: CERTAINTY Methodology and prototypes.\nThe impact of CERTAINTY will be to contribute to the certification of mixed criticality applications on multi cores in more efficient and effective ways (performance improvement regarding strict temporal partitioning), and provide recommendations to standardization working groups preparing the way for new standards in this area.

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