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News Article | March 24, 2016
Site: www.scientificcomputing.com

In aerospace, automation and automotive technologies, smart electronic computer systems have to meet a number of security and real-time requirements. In case of critical incidents, for instance, the software’s response time has to be very short. Programming of the corresponding applications is time- and cost-consuming. Partners of industry and research are now developing a tool chain for efficient, standardized, and real-time-capable programming under the EU consortium ARGO that is coordinated by Karlsruhe Institute of Technology (KIT). Development is based on the open source software Scilab. More and more safety-critical embedded electronic solutions are based on rapid, energy-efficient multicore processors. “Two of the most important requirements of future applications are an increased performance in real time and further reduction of costs without adversely affecting functional safety,” Professor Jürgen Becker of the Institute for Information Processing Technology (ITIV) of KIT says, who coordinates ARGO. “For this, multicore processors have to make available the required performance spectrum at minimum energy consumption in an automated and efficiently programmed manner.” Multicore systems are characterized by the accommodation of several processor cores on one chip. The cores work in parallel and, hence, reach a higher speed and performance. Programming of such heterogeneous multicore processors is very complex. Moreover, the programs have to be tailored precisely to the target hardware and to fulfill the additional real-time requirements. The ARGO EU research project, named after the very quick vessel in Greek mythology, is aimed at significantly facilitating programming by automatic parallelization of model-based applications and code generation. So far, a programmer had to adapt his code, i.e. the instructions for the computer, to the hardware architecture, which is associated with a high expenditure and prevents the code from being transferred to other architectures. “Under ARGO, a new standardizable tool chain for programmers is being developed. Even without precise knowledge of the complex parallel processor hardware, the programmers can control the process of automatic parallelization in accordance with the requirements. This results in a significant improvement of performance and a reduction of costs,” Becker says. In the future, the ARGO tool chain can be used to manage the complexity of parallelization and adaptation to the target hardware in a largely automated manner with a small expenditure. Under the project, real-time-critical applications in the areas of real-time flight dynamics simulation and real-time image processing are studied and evaluated by way of example. Eight project partners of science and industry cooperate under the project: Apart from KIT, the University of Rennes (France), the Technological Educational Institute of Western Greece, the German Aerospace Center, and the Fraunhofer Institute for Integrated Circuits IIS (Germany) as well as Recore Systems B.V. (the Netherlands), Scilab Enterprises (France), and AbsInt Angewandte Informatik GmbH (Germany) are involved in ARGO. “ARGO — WCET-aware Parallelization of Model-based Applications for Heterogeneous Parallel Systems” will be funded by the EU with EUR 3.9 million in the next three years. The project is coordinated by Professor Jürgen Becker, Head of the Institute for Information Processing Technology (ITIV) of KIT.

Kastner D.,AbsInt Angewandte Informatik GmbH | Jersak M.,Symtavision | Ferdinand C.,AbsInt Angewandte Informatik GmbH | Gliwa P.,Gliwa GmbH | Heckmann R.,AbsInt Angewandte Informatik GmbH
SAE Technical Papers | Year: 2011

Developers of safety-critical real-time systems have to ensure that their systems react within given time bounds. Ideally, the system is designed to provide sufficient computing power and network bandwidth, is cost efficient and provides the necessary safety level. To achieve this goal, three challenges have to be addressed. First, it must be possible to account for timing during early development stages in the architecture exploration phase. Second, during software development, timing behavior and the effects of software changes on timing must be observable. Third, there must be a technology for formally verifying the final timing behavior for industry-size applications. In this article we present a comprehensive methodology for dealing with timing which addresses all three issues based on state-of-the-art commercial tools. AbsInt's TimingExplorer provides execution time estimates for an early code-level ECU exploration, while Symtavision's SymTA/S Architecture Explorer provides execution time budgets for the selected hardware and software at the system level. Gliwa T1 can deliver measurement-based information about the worst-case execution time of basic blocks, the core execution time and the response time of tasks and interrupts. AbsInt's aiT is a static analyzer which determines safe upper bounds for the worst-case execution times of non-interrupted tasks. It can be used during software development as a part of the build process and at the validation stage to provide guaranteed WCET bounds. Both task-level analysis results and measurement information can be fed into the system-level analysis tool SymTA/S from Symtavision, which computes the worst-case response times (WCRTs) of the entire system. For an efficient, integrated flow, all these tools share a common abstraction level and are coupled by well-defined interfaces. Starting from a system model, designers can now seamlessly perform timing budgeting, monitor and observe timing during software development, and do performance optimization and timing verification. This is possible both on the code of individual functions, as well as for function and subsystem integration. Copyright © 2011 SAE International.

Di Natale M.,Scuola S. Anna | Gai P.,Evidence Srl | Heckmann R.,Absint Angewandte Informatik Gmbh | Ferdinand C.,Absint Angewandte Informatik Gmbh | And 5 more authors.
SAE Technical Papers | Year: 2010

Modern automotive embedded systems are characterized by timing constraints at different levels in the design hierarchy and flow. System-level functions like modern active-safety functions are characterized by end-to-end constraints that span several ECUs and buses. ECU-level functions, like fuel injection controls need to cope with stringent resource requirements, tight time constraints and event-driven computations with different execution modes. This paper introduces some of the models, the techniques and the tool integration methods developed in the context of the INTERESTED project to guarantee timing correctness at all levels in the flow. In addition, we outline the issues arising from the application of these techniques to a fuel injection case study. Finally, we also discuss the implications in the integration/compatibility of the proposed flow with existing standards, like UML with the MARTE profile and AUTOSAR, and widely used commercial products, like Simulink and its code generator companion tools. Copyright © 2010 SAE International.

Kaestner D.,AbsInt Angewandte Informatik GmbH | Rustemeier C.,DSPACE GmbH | Kiffmeier U.,DSPACE GmbH | Fleischer D.,DSPACE GmbH | And 4 more authors.
SAE Technical Papers | Year: 2014

Model-based development is the established way of developing embedded control algorithms, especially for safety-critical applications. The aim is to improve development efficiency and safety by developing the software at a high abstraction level (the model) and by generating the implementation (the C code) automatically from the model. Although model-based development focuses on the models themselves, downstream artifacts such as source code or executable object code have to be considered in the verification stage. Safety standards such as ISO 26262 require upper bounds to be determined for the required storage space or the execution time of real-time tasks, and the absence of run-time errors to be demonstrated. Static analysis tools are available which work at the code level and can prove the absence of such errors. However, the connection to the model level has to be explicitly established. In this article we present an approach to integrate static code analyzers with model-based development tools. The static analysis can be invoked automatically from the modeling tool with relevant model-level information automatically being propagated to the analyzer to optimize analysis precision. The results are mapped back to the modeling level. This way, timing bugs, stack overflows, and run-time errors can be detected early in the development process. Implementation-level errors can be traced back to the modeling level, and can be investigated at both the model and the implementation level. This significantly reduces the development effort and allows bugs to be detected early in the development process. Copyright © 2014 SAE International.

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