Jansen R.J.E.,European Space Agency |
Haanstra J.,Dialog Semiconductors |
European Solid-State Circuits Conference | Year: 2012
This paper describes the design of an accurate and simple static complementary constant-gm biasing circuit for Nauta's transconductors in low-power low-frequency CMOS gm-C bandpass filters and their optimization and trimming for process and temperature independent filter performance. Experimental results are presented for a prototype 3rd order Butterworth bandpass filter in a 180nm CMOS process with a 2MHz bandwidth and centre frequency. These filters are appropriate for the channel selection stage of a Zigbee receiver and show with a single trim for process over a 80C temperature range only a 2% deviation in the bandwidth and centre frequency. © 2012 IEEE.
Essel J.,Technologies |
Brenk D.,Technologies |
Heidrich J.,Alcatel - Lucent |
Weigel R.,Friedrich - Alexander - University, Erlangen - Nuremberg |
Kissinger D.,Friedrich - Alexander - University, Erlangen - Nuremberg
IEEE Transactions on Microwave Theory and Techniques | Year: 2013
This work focuses on the comprehensive measurement-based nonlinear characterization of an integrated analog frontend, which is implemented into a passive multifunctional radio-frequency-identification (RFID) transponder. It explains the necessity and the practical execution of large-signal characterization and nonlinear analyses of the frontend at ultra-high- frequencies. The fundamentals of the implemented source-pull measurement setup are described in detail and the results of selected measurements are presented. To the authors knowledge, this is the first time that a passive RFID frontend is characterized by nonlinear large-signal measurements. © 1963-2012 IEEE.
Reviriego P.,Antonio de Nebrija University |
Pontarelli S.,University of Rome Tor Vergata |
Evans A.,Technologies |
Maestro J.A.,Antonio de Nebrija University
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2015
Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay. © 1993-2012 IEEE.