9 Heroon Polytechneiou

Athens, Greece

9 Heroon Polytechneiou

Athens, Greece

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Sidiropoulos H.,9 Heroon Polytechneiou | Siozios K.,9 Heroon Polytechneiou | Soudris D.,9 Heroon Polytechneiou
Journal of Systems Architecture | Year: 2013

This paper introduces a novel methodology for enabling fast yet accurate exploration of memory organizations onto FPGA devices. The proposed methodology is software supported by a new open-source tool framework, named NAROUTO. This framework is the only public available solution for performing architecture-level exploration, as well as application mapping onto FPGA devices with different memory organizations, under a variety of design criteria (e.g. delay improvement, power optimization, area savings, etc.). Experimental results with a number of industrial oriented kernels prove the efficiency of the proposed solution, as compared to similar approaches, since it provides better manipulation of memory blocks, leading to architectures with higher performance in terms of area, power and delay. © 2012 Elsevier B.V. All rights reserved.


Sidiropoulos H.,9 Heroon Polytechneiou | Siozios K.,9 Heroon Polytechneiou | Soudris D.,9 Heroon Polytechneiou
Journal of Systems Architecture | Year: 2014

The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. The demand for even higher clock frequencies makes this problem even more important. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. However, the benefits of such a new integration paradigm have not been sufficiently explored yet. In this paper, a novel 3-D architecture, as well as the software supporting tools for exploring and evaluating application implementation, are introduced. More specifically, by assigning to different layers logic and I/O resources, we achieve mentionable wire-length reduction. Experimental results prove the effectiveness of such a selection, since target architectures outperform the conventional 2-D FPGAs. © 2013 Elsevier B.V. All rights reserved.

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