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Time filter

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Edmonton, Canada

Alimohammad A.,San Diego State University | Fouladi Fard S.,4344 Enterprise Square | Cockburn B.F.,University of Alberta
IET Communications | Year: 2012

The accurate simulation of wireless channels is important since it permits the realistic and repeatable performance measurement of wireless systems. A new technique is proposed for simulating Rayleigh fading channels with isotropic or non-isotropic scattering and with arbitrary temporal correlation. Fading samples are generated by passing Gaussian samples through a spectrum shaping filter. A new iterative algorithm is then presented for designing stable complex infinite impulse response (IIR) filters with quantised coefficients. The algorithm utilises a least-squares cost function augmented with a barrier function to ensure filter stability and to reduce quantisation noise. The performance of the proposed filter design algorithm is verified with 18-bit fixed-point simulations of different fading channel scenarios including isotropic and non-isotropic scattering and the IEEE 802.11n model F fading spectrum. © 2012 The Institution of Engineering and Technology. Source


Alimohammad A.,San Diego State University | Fard S.F.,4344 Enterprise Square | Cockburn B.F.,University of Alberta
Modelling and Simulation in Engineering | Year: 2012

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. A key technique for producing statistically accurate fading variates is to shape the flat spectrum of Gaussian variates using digital filters. This paper addresses various challenges when designing real and complex spectrum shaping filters with quantized coefficients for efficient realization of both isotropic and nonisotropic fading channels. An iterative algorithm for designing stable complex infinite impulse response (IIR) filters with fixed-point coefficients is presented. The performance of the proposed filter design algorithm is verified with 16-bit fixed-point simulations of two example fading filters. © 2012 Amirhossein Alimohammad et al. Source


Fard S.F.,4344 Enterprise Square | Alimohammad A.,4344 Enterprise Square | Cockburn B.F.,University of Alberta
IET Communications | Year: 2011

The authors propose a compact and fast fading channel simulator for the baseband verification and prototyping of multiple-input multiple-output (MIMO) wireless communication systems. The simulator accurately and efficiently implements models of both single-bounce and multiple-bounce geometric propagation conditions. Fading samples are generated at a low rate, comparable to the Doppler frequency, and then interpolated to match the desired sample rate. Bit-true simulations verify the accuracy of the hardware simulator. As an example, when implemented on a Xilinx XC5VLX110 field-programmable gate array (FPGA), the 4×4 MIMO geometric fading channel simulator occupies only 6.6% of the configurable slices while generating more than 16×324 million samples per second. The geometric MIMO fading channel simulator is well suited for use in an FPGA-based error rate performance verification system. © 2011 The Institution of Engineering and Technology. Source


Alimohammad A.,4344 Enterprise Square | Fard S.F.,4344 Enterprise Square | Cockburn B.F.,University of Alberta
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2011

Compact and fast implementations of digital Rayleigh and Ricean variate generators are presented. Polynomial curve fitting is utilized along with a combination of logarithmic and uniform domain segmentation to provide accuracy, compactness and fast variate generation. A typical instantiation of the proposed Rayleigh generator occupies 124 (< 1%) of the configurable slices, two dedicated multipliers (< 1%), and one on-chip block memory (< 1%) of a Xilinx Virtex-5 field-programmable gate array (FPGA) and operates at 317 MHz, generating 317 million Rayleigh variates per second. The Ricean variate generator implementation on the same device utilizes 366 (< 1%) of the logical slices, three on-chip block memories (< 1%), and 11 (2.8%) of the dedicated multipliers. The application of the Rayleigh and Ricean variate generators is demonstrated in a FPGA-based bit error rate simulator that measures at hardware speeds the symbol error rate performance of a typical wireless communication system over Rayleigh and Ricean fading channels. © 2010 IEEE. Source


Alimohammad A.,4344 Enterprise Square | Fard S.F.,4344 Enterprise Square | Cockburn B.F.,University of Alberta
IET Communications | Year: 2011

This article presents an ultra-compact and high-throughput reconfigurable fading channel simulator that supports a relatively large number of propagation paths. To closely reflect actual radio channels, the authors used a recently improved Rayleigh and Ricean fading channel model based on the sum-of-sinusoids technique. The improved model is optimised for hardware compactness. To achieve a fast fading variate generation rate with much less hardware and no significant loss in accuracy, the new scheme first generates fading samples at a lower rate using a time-multiplexed datapath that can be fit into a small fraction of a field-programmable gate array (FPGA). In the second step, the simulator uses a compact multiplication-free linear interpolator to produce the fading samples at the full symbol rate. Implementing a 64-path fading channel simulator on a Xilinx Virtex-4 XC4VLX200-11 FPGA requires only 13 044 (14%) of the configurable slices, 10 (2%) of the block memories and one (1%) of the dedicated DSP blocks, while generating 64 × 191 million complex-valued fading samples per second. The simulated paths can be readily combined to form high path count models for multiple-input multiple-output systems as well as frequency-selective channels. © 2011 The Institution of Engineering and Technology. Source

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