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Taoyuan City, Taiwan

Lee Y.-H.,135 Yuan Tung Road | Pan C.-W.,135 Yuan Tung Road
Journal of Signal Processing Systems

The Dedicated Short-Range Communication (DSRC) is an emerging standard to push the vehicular communication into modern automotive industry. The DSRC standard generally applies FM0 and Manchester to reach DC-balance enhancing the signal reliability. However, the intrinsic unbalance computation load between FM0 and Manchester makes their VLSI architecture with poor hardware utilization. In this paper, the reuse-oriented Boolean simplification (ROBS) technique is proposed to overcome this problem. The ROBS technique constructs the balance-type architecture to improve the hardware utilization rate (HUR) from 50 % to 90 %. The analysis of how the clock-skew affects the balance-type architecture is also discussed. This work is realized by 0.18um 1P6M CMOS technology with cell-based design flow. The gate count is 25.61, which is normalized to a 2-input NAND gate. The power consumption is 6.58uW@27MHz for FM0 encoding and 6.85uW@27MHz for Manchester encoding. The encoding capability is up to 27 Mbps that can fully support the DSRC standards of America, Europe and Japan. © 2013, Springer Science+Business Media New York. Source

Lee Y.-H.,135 Yuan Tung Road | Chen C.-C.,135 Yuan Tung Road | You Y.-L.,135 Yuan Tung Road
Circuits, Systems, and Signal Processing

In this paper, an autocorrelation-based lossless recompression (ABLR) algorithm is proposed. The ABLR can save the memory bandwidth of video coding systems and preserves the visual quality. The ABLR consists of two core techniques: (1) a correlation-based prediction technique and (2) a correlation-adaptive Golomb-Rice code. Furthermore, dual-mode memory addressing (DMMA) is also proposed to provide ABLR with memory random access functionality. The word-length utilization rate (WLUR) of DMMA is as high as 92.34 % on average. The experimental results reveal that the ABLR exhibits a lossless compression ratio of 2.05 on average for 1080p test sequences. This indicates that the memory bandwidth can be saved up to 50 %. The VLSI architecture of ABLR is designed with three-stage pipelining and is realized in 0.18 μm 1P6M CMOS technology with a cell-based design flow. The logic gate count is about 28 K and the core area is 0.69×0.68 mm2. The encoding capability can reach full HD (1920×1080)@30 fps at a clock rate of 62.5 MHz. The power dissipation is 9.35 mW at a clock rate of 62.5 MHz. © 2013 Springer Science+Business Media New York. Source

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